Custom IC Design

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Discussion

Replace symbol pin names without changing the pin placement and symbol boundary

Category: Custom IC Design

By SimhanAnalog

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updated 4 days ago by SimhanAnalog

4 replies • 657 views
Discussion

plotting results does not properly work

Category: Custom IC Design

By TommasoF

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updated 4 days ago by TommasoF

3 replies • 219 views
Discussion

Which simulation tools are supported for Voltus-XFi within Virtuoso environment?

Category: Custom IC Design

By JY202510312553

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started 4 days ago

0 replies • 76 views
Discussion

TSMC PDK Inductor Finder

Category: Custom IC Design

By nqthang

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started 5 days ago

0 replies • 125 views
Discussion

Fundamental question on edge phase noise from sampled PNOISE

Category: Custom IC Design

By Yuto Lau

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updated 5 days ago by Yuto Lau

6 replies • 481 views
Discussion

PWM block gain simulation using pss

Category: Custom IC Design

By TH202510293247

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started 5 days ago

0 replies • 100 views
Discussion

Cadence Virtuoso IC6.1.8 - Layout GXL Automatic Placement

Category: Custom IC Design

By hoangtn3702

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started 6 days ago

0 replies • 110 views
Discussion

wait a long time to have results updated

Category: Custom IC Design

By sjwprcssw

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started 7 days ago

0 replies • 165 views
Discussion

SOA analysis in cadence virtuoso

Category: Custom IC Design

By TUKA

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started 8 days ago

0 replies • 149 views
Discussion

Strategy for Accelerating Full-Chip AMS Simulation with Multi-Rate Clocks (1kHz / 100MHz)

Category: Custom IC Design

By HY202510149941

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updated 8 days ago by Alonso Schmidt

1 replies • 322 views
Discussion

Buses in spectreText when creating symbol

Category: Custom IC Design

By MC20250412421

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updated 9 days ago by MC20250412421

2 replies • 324 views
Discussion

Does Cadence provide a standard Python API for tool automation?

Category: Custom IC Design

By WM20250906725

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updated 12 days ago by Andrew Beckett

5 replies • 2229 views
Discussion

Issue with Skywater 130 Monte Carlo Mismatch Analysis

Category: Custom IC Design

By VLSI lab IITB

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updated 13 days ago by VLSI lab IITB

2 replies • 447 views
Discussion

Issue with the ADE Explorer/Assembler simulator

Category: Custom IC Design

By GL202502244954

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started 14 days ago

0 replies • 157 views
Discussion

Date/time (or $system) in verilogA

Category: Custom IC Design

By leok

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updated 15 days ago by leok

2 replies • 270 views

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