Custom IC Design

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Discussion

spectre save command - usage

Category: Custom IC Design

By roopakvasa

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updated over 6 years ago by Andrew Beckett

1 replies • 3725 views
Discussion

Generating Device In Schematic From Layout

Category: Custom IC Design

By FormerMember

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updated over 6 years ago by Andrew Beckett

1 replies • 2625 views
Discussion

how to load skill script in the icrp without .cdsinit

Category: Custom IC Design

By YiWang

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updated over 6 years ago by YiWang

2 replies • 14852 views
Discussion

Quantus: warning regarding separate field solver techfile with MEOL stack description

Category: Custom IC Design

By dontpanic

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updated over 6 years ago by dontpanic

2 replies • 13476 views
Discussion

QRC: extraction fails due to ports names including the "+" character

Category: Custom IC Design

By dontpanic

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updated over 6 years ago by dontpanic

2 replies • 1892 views
Discussion

Import Schematic from Mentor Tanner to Cadence

Category: Custom IC Design

By HwDoesThisWork

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updated over 6 years ago by Andrew Beckett

10 replies • 18454 views
Discussion

Liberate - Custom Cell Characterization

Category: Custom IC Design

By manpmanp

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updated over 6 years ago by anurans

1 replies • 1893 views
Discussion

Plotting transistor parameters in a temperature sweep

Category: Custom IC Design

By CADcasualty

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updated over 6 years ago by CADcasualty

2 replies • 15885 views
Discussion

Fix "tool tip" colors in GNOME

Category: Custom IC Design

By dontpanic

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updated over 6 years ago by dontpanic

2 replies • 2535 views
Discussion

how to setup connectivity between layout and schematic

Category: Custom IC Design

By Amit yadav

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updated over 6 years ago by skillUser

1 replies • 16408 views
Discussion

VerilogA parsing problem

Category: Custom IC Design

By StanleyN

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updated over 6 years ago by subramanya007

4 replies • 16835 views
Discussion

Input .csv file for ADE L simulation sampling error

Category: Custom IC Design

By BigJim

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updated over 6 years ago by BigJim

3 replies • 14284 views
Discussion

Calibre fails to export schematic netlist

Category: Custom IC Design

By mhawary85

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updated over 6 years ago by Andrew Beckett

5 replies • 26119 views
Discussion

is it possible to extract the subcircuit names/models and the associated pins from input.scs ?

Category: Custom IC Design

By marcelpreda

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updated over 6 years ago by marcelpreda

4 replies • 2449 views
Discussion

DC-DC Converter/ Feedback/ Verilog-A

Category: Custom IC Design

By Pyroblast

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updated over 6 years ago by nnlt

40 replies • 39023 views

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