Custom IC Design

Latest Posts

Discussion

Drawing with Viva

Category: Custom IC Design

By BradW

$usertype
•
updated over 13 years ago by Andrew Beckett

1 replies • 15542 views
Discussion

IC6.14, Issues with Hierarchy in schematics

Category: Custom IC Design

By Kabal

$usertype
•
updated over 13 years ago by Kabal

2 replies • 15606 views
Discussion

IBM_PDK 7RF, IC6.14, Extraction of circuit

Category: Custom IC Design

By Kabal

$usertype
•
updated over 13 years ago by Kabal

5 replies • 14707 views
Discussion

Problem with cdsdoc (version2.1) of hotfix IC 5141

Category: Custom IC Design

By RAO VINAY

$usertype
•
updated over 13 years ago by RAO VINAY

6 replies • 15853 views
Discussion

How transient operating point is calculated in cadence

Category: Custom IC Design

By prashu

$usertype
•
updated over 13 years ago by imagesensor123

27 replies • 36158 views
Discussion

mapping logical libraries in AMS Designer (VHDL)

Category: Custom IC Design

By FedericoPI

$usertype
•
updated over 13 years ago by FedericoPI

7 replies • 18061 views
Discussion

how to simulate device noise when the circuit has chopping block

Category: Custom IC Design

By kunmingcai

$usertype
•
updated over 13 years ago by Andrew Beckett

3 replies • 15657 views
Discussion

PDK update

Category: Custom IC Design

By Aram Shahinyan

$usertype
•
updated over 13 years ago by Aram Shahinyan

2 replies • 14766 views
Discussion

Corner Analysis with IC6.1.3 and AMS HIT-Kit v4.00

Category: Custom IC Design

By dineshp

$usertype
•
updated over 13 years ago by dineshp

2 replies • 15453 views
Discussion

Biasing technics for Diffpair(or opamp)

Category: Custom IC Design

By venuuuuu

$usertype
•
updated over 13 years ago by Quek

1 replies • 798 views
Discussion

vpwlf error: Time is not strictly increasing

Category: Custom IC Design

By surreyian

$usertype
•
updated over 13 years ago by surreyian

6 replies • 20862 views
Discussion

Illogical outputs from cadence (IC5141) ADE.

Category: Custom IC Design

By RAO VINAY

$usertype
•
updated over 13 years ago by RAO VINAY

2 replies • 14082 views
Discussion

How to Find the drawn net("MET1" "drawing") in the layout.

Category: Custom IC Design

By ShrikantTI

$usertype
•
updated over 13 years ago by Andrew Beckett

4 replies • 2851 views
Discussion

Assura LVS: Clarification on virtual connection using joinablePin() function.

Category: Custom IC Design

By ShrikantTI

$usertype
•
updated over 13 years ago by Quek

1 replies • 15455 views
Discussion

effective length variation after Monte Carlo trial

Category: Custom IC Design

By inessadm

$usertype
•
updated over 13 years ago by Andrew Beckett

6 replies • 16152 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.