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Custom IC Design

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  • Discussion

    Replace symbol pin names without changing the pin placement and symbol boundary

    Category: Custom IC Design

    By SimhanAnalog

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    updated 1 month ago by SimhanAnalog

    4 replies • 1262 views
  • Discussion

    Which simulation tools are supported for Voltus-XFi within Virtuoso environment?

    Category: Custom IC Design

    By JY202510312553

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    •

    started 1 month ago

    0 replies • 467 views
  • Discussion

    TSMC PDK Inductor Finder

    Category: Custom IC Design

    By nqthang

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    started 1 month ago

    0 replies • 617 views
  • Discussion

    Fundamental question on edge phase noise from sampled PNOISE

    Category: Custom IC Design

    By Yuto Lau

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    •

    updated 1 month ago by Yuto Lau

    6 replies • 1024 views
  • Discussion

    PWM block gain simulation using pss

    Category: Custom IC Design

    By TH202510293247

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    •

    started 1 month ago

    0 replies • 384 views
  • Discussion

    Cadence Virtuoso IC6.1.8 - Layout GXL Automatic Placement

    Category: Custom IC Design

    By hoangtn3702

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    started 1 month ago

    0 replies • 206 views
  • Discussion

    wait a long time to have results updated

    Category: Custom IC Design

    By sjwprcssw

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    •

    started 1 month ago

    0 replies • 500 views
  • Discussion

    SOA analysis in cadence virtuoso

    Category: Custom IC Design

    By TUKA

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    started 1 month ago

    0 replies • 513 views
  • Discussion

    Strategy for Accelerating Full-Chip AMS Simulation with Multi-Rate Clocks (1kHz / 100MHz)

    Category: Custom IC Design

    By HY202510149941

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    •

    updated 1 month ago by Alonso Schmidt

    1 replies • 729 views
  • Discussion

    Buses in spectreText when creating symbol

    Category: Custom IC Design

    By MC20250412421

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    •

    updated 1 month ago by MC20250412421

    2 replies • 751 views
  • Discussion

    Does Cadence provide a standard Python API for tool automation?

    Category: Custom IC Design

    By WM20250906725

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    •

    updated 1 month ago by Andrew Beckett

    5 replies • 3373 views
  • Discussion

    Issue with the ADE Explorer/Assembler simulator

    Category: Custom IC Design

    By GL202502244954

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    •

    started 1 month ago

    0 replies • 248 views
  • Discussion

    Date/time (or $system) in verilogA

    Category: Custom IC Design

    By leok

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    •

    updated 1 month ago by leok

    2 replies • 454 views
  • Discussion

    quantus parasitic extraction vs. SKY130 PDK

    Category: Custom IC Design

    By GS202507021424

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    •

    updated 1 month ago by Andrew Beckett

    2 replies • 1933 views
  • Discussion

    Quantus Error – Sky130 qrcTechFile not recognized as valid technology file

    Category: Custom IC Design

    By RK202509013321

    $usertype

    •

    updated 1 month ago by Andrew Beckett

    1 replies • 1035 views
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