Custom IC Design

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Discussion

Bind key to change Path end type(ex:extend,truncate,round,variable)

Category: Custom IC Design

By KarthikJaiho

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updated over 11 years ago by KarthikJaiho

2 replies • 1598 views
Discussion

Importing .gds file in virtuoso

Category: Custom IC Design

By RFStuff

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updated over 11 years ago by RFStuff

2 replies • 14954 views
Discussion

How to create layout xl for user defined pcell with same parameters as in schematic??

Category: Custom IC Design

By KarthikJaiho

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updated over 11 years ago by Andrew Beckett

1 replies • 13084 views
Discussion

Abstract Generator : 2 layouts of a same "Memory instance" identified as "Block" and "Core" why ?

Category: Custom IC Design

By samung

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updated over 11 years ago by ColinSutlieff

1 replies • 989 views
Discussion

Netlist error when simulating BSIMCMG

Category: Custom IC Design

By Chen23

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updated over 11 years ago by Chen23

1 replies • 15753 views
Discussion

ABSTRACT GENERATOR : absSelectCell for a multi-cells Library, syntax ?

Category: Custom IC Design

By samung

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updated over 11 years ago by samung

2 replies • 13316 views
Discussion

Design rules for library TSMC 0.18U CMOS 018 DEEP (6M, HV FET, S block)

Category: Custom IC Design

By rajrevanth61

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updated over 11 years ago by ColinSutlieff

1 replies • 16560 views
Discussion

connect all the bus lines together

Category: Custom IC Design

By Clidre

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updated over 11 years ago by FormerMember

3 replies • 18549 views
Discussion

Convergence problem in MC simulations

Category: Custom IC Design

By Flyyn Rider

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updated over 11 years ago by Andrew Beckett

1 replies • 12934 views
Discussion

cadence virtuoso available utilities

Category: Custom IC Design

By auto dipper

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updated over 11 years ago by FormerMember

7 replies • 15534 views
Discussion

Bindkey to change via (ex:M1_M2 to M2_M3)

Category: Custom IC Design

By KarthikJaiho

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updated over 11 years ago by Andrew Beckett

3 replies • 1231 views
Discussion

PVS - Cadence Physical Verification System

Category: Custom IC Design

By Kovinko

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updated over 11 years ago by Andrew Beckett

1 replies • 2149 views
Discussion

av_analog extracted fom Calibre PEX

Category: Custom IC Design

By Nicusor

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updated over 11 years ago by Andrew Beckett

1 replies • 13297 views
Discussion

Assura LVS errors

Category: Custom IC Design

By RFStuff

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updated over 11 years ago by Andrew Beckett

1 replies • 13411 views
Discussion

AbstractBlockageCoverLayers on not flatten memory instance

Category: Custom IC Design

By samung

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updated over 11 years ago by samung

5 replies • 14498 views

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