Custom IC Design

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PVS LVS not flagging device W/L mismatches in gpdk045 (IC23.1 / PVS 23.11)

Category: Custom IC Design

By RK202509013321
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updated 10 days ago by Andrew Beckett

6 replies • 940 views
Discussion

ADE Explorer Design Variables sweep sets for Cadence PDK FinFet mosfet multiplier

Category: Custom IC Design

By hesaliveJim
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updated 11 days ago by Andrew Beckett

3 replies • 792 views
Discussion

How to use "config" or other methods to switch the cell's library during simulation

Category: Custom IC Design

By dogman4
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updated 12 days ago by dogman4

4 replies • 626 views
Discussion

Cannot obtain the license for spectreRF when interfacing matlab with spectre

Category: Custom IC Design

By SW202509035411
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updated 12 days ago by SW202509035411

17 replies • 1342 views
Discussion

Quantus QRC issue

Category: Custom IC Design

By HY20250821344
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updated 12 days ago by HY20250821344

2 replies • 648 views
Discussion

Could not find netlist procedure:SpectreFNPairs instance

Category: Custom IC Design

By ranaya
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updated 13 days ago by Andrew Beckett

5 replies • 775 views
Discussion

LUT implementation using VerilogA code In Cadence Virtuoso

Category: Custom IC Design

By ZulfiqarKiani
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started 13 days ago

0 replies • 427 views
Discussion

Sorting variables by name alphanumerically in Virtuoso ADE Assembler / maestro

Category: Custom IC Design

By Dominique8765
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updated 14 days ago by Andrew Beckett

1 replies • 250 views
Discussion

sweeping transistor number of fingers in a simulation

Category: Custom IC Design

By TommasoF
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updated 14 days ago by TommasoF

2 replies • 712 views
Discussion

xrun: *F,SROOTE: Cannot find the Spectre installation

Category: Custom IC Design

By Leo 93
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updated 16 days ago by Andrew Beckett

3 replies • 478 views
Discussion

use DC sweep variable to set another variable

Category: Custom IC Design

By Darrell L
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updated 16 days ago by Darrell L

2 replies • 485 views
Discussion

automate cadence design to avoid time consuming steps for simulation using python subprocess module.

Category: Custom IC Design

By AP202507218251
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started 16 days ago

0 replies • 249 views
Discussion

ERROR (NVN-13010): Cell rupolym is not defined while running Pegasus LVS

Category: Custom IC Design

By yogeshjaiswalCAD
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updated 17 days ago by Andrew Beckett

3 replies • 425 views
Discussion

All pins on schematics unconnected to their attached wires when importing EDIF from Siemens,

Category: Custom IC Design

By DavidGogiber
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updated 18 days ago by Andrew Beckett

4 replies • 753 views
Discussion

Cannot Copy Variable to Other Tests

Category: Custom IC Design

By MM202507017815
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updated 20 days ago by Andrew Beckett

1 replies • 351 views

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