Custom IC Design

Latest Posts

Discussion

Error while streaming GDS file into Virtuoso

Category: Custom IC Design

By medeepak

$usertype
•
updated over 13 years ago by Quek

1 replies • 15013 views
Discussion

Use hspice to simulate a spectre netlist

Category: Custom IC Design

By ycau

$usertype
•
updated over 13 years ago by Andrew Beckett

1 replies • 14147 views
Discussion

Errors while loading virtuoso (HitKit)

Category: Custom IC Design

By pitter

$usertype
•
updated over 13 years ago by Hesham2012

8 replies • 17757 views
Discussion

Many globals with its own voltage

Category: Custom IC Design

By StreamCX

$usertype
•
updated over 13 years ago by Andrew Beckett

3 replies • 5498 views
Discussion

saving operating point parameters

Category: Custom IC Design

By soathana

$usertype
•
updated over 13 years ago by soathana

2 replies • 13912 views
Discussion

Practical limit to the number of elements in a vector port in VerilogA

Category: Custom IC Design

By Herge

$usertype
•
updated over 13 years ago by Andrew Beckett

1 replies • 13068 views
Discussion

How to use Tcl command to get expression value from a AMS simulation?

Category: Custom IC Design

By greatqs

$usertype
•
updated over 13 years ago by Andrew Beckett

6 replies • 17918 views
Discussion

2011 Models for TSMC RF90NM

Category: Custom IC Design

By JustinTaylor86

$usertype
•
updated over 13 years ago by Andrew Beckett

8 replies • 15055 views
Discussion

out-of-context probing

Category: Custom IC Design

By BradW

$usertype
•
updated over 13 years ago by Andrew Beckett

1 replies • 14188 views
Discussion

Virtuoso does not save certain nodes during transient simulation

Category: Custom IC Design

By Wonyoung

$usertype
•
updated over 13 years ago by Andrew Beckett

1 replies • 14834 views
Discussion

Custom Netlisting in ADE

Category: Custom IC Design

By GaneshShamnur

$usertype
•
updated over 13 years ago by Andrew Beckett

4 replies • 13366 views
Discussion

save data from outputs

Category: Custom IC Design

By surreyian

$usertype
•
updated over 13 years ago by Andrew Beckett

1 replies • 13475 views
Discussion

Undo pcell

Category: Custom IC Design

By RVERP

$usertype
•
updated over 13 years ago by RVERP

2 replies • 13670 views
Discussion

Parasitic devices/probes in the schematic --> How to fix the layout connectivity (flightlines) in VXL?

Category: Custom IC Design

By Wim Verhaegen

$usertype
•
updated over 13 years ago by Wim Verhaegen

4 replies • 2009 views
Discussion

how to activate/deactivate a component during a simulation

Category: Custom IC Design

By wighou

$usertype
•
updated over 13 years ago by Andrew Beckett

4 replies • 5812 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.