Custom IC Design

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ERROR (NVN-13010): Cell rupolym is not defined while running Pegasus LVS

Category: Custom IC Design

By yogeshjaiswalCAD

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updated 1 month ago by Andrew Beckett

3 replies • 802 views
Discussion

All pins on schematics unconnected to their attached wires when importing EDIF from Siemens,

Category: Custom IC Design

By DavidGogiber

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updated 1 month ago by Andrew Beckett

4 replies • 1084 views
Discussion

Cannot Copy Variable to Other Tests

Category: Custom IC Design

By MM202507017815

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updated 1 month ago by Andrew Beckett

1 replies • 612 views
Discussion

Cadence PEX Directory Creation - Unable to Create the Directory for Netlist

Category: Custom IC Design

By ranaya

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updated 1 month ago by ranaya

2 replies • 508 views
Discussion

Cadence Parasitic Extraction - Location / Directory Issue

Category: Custom IC Design

By ranaya

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updated 1 month ago by Andrew Beckett

1 replies • 353 views
Discussion

Automating Library Reference Change with Additional Parameters in New Library

Category: Custom IC Design

By AN202507174258

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started 1 month ago

0 replies • 576 views
Discussion

For a new machine, which RHEL?

Category: Custom IC Design

By kenc184

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updated 1 month ago by kenc184

3 replies • 982 views
Discussion

Parameterization of transistor model BSIM4 parameters

Category: Custom IC Design

By Sourav Chakraborty

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started 1 month ago

0 replies • 595 views
Discussion

Verilog A: Generate different $random values for each Monte Carlo iteration

Category: Custom IC Design

By MC20250412421

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updated 2 months ago by MC20250412421

6 replies • 1408 views
Discussion

Convert Cadence Spectre to Cadence Orcad

Category: Custom IC Design

By SC202412036016

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started 2 months ago

0 replies • 740 views
Discussion

Voltus-Fi-XL : generated path of mergedCurrents.rpt

Category: Custom IC Design

By SY202508201356

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started 2 months ago

0 replies • 720 views
Discussion

setting environment variables from schematic?

Category: Custom IC Design

By unSkilled

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started 2 months ago

0 replies • 678 views
Discussion

STB Analysis Breakpoint Selection and Nyquist Plot Support in Cadence

Category: Custom IC Design

By Eleanor Grace

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updated 2 months ago by JankoK

3 replies • 1154 views
Discussion

stb results different when iprobe placed at different location of the loop

Category: Custom IC Design

By a048

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updated 2 months ago by Frank Wiedmann

3 replies • 1155 views
Discussion

giolib045 "archaeology" (origin of giolib045.lib, giolib045.gds files)

Category: Custom IC Design

By GS202507021424

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started 2 months ago

0 replies • 321 views

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