Custom IC Design

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Discussion

Guidelines for the Custom IC Design Forum

Category: Custom IC Design

By Andrew Beckett

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started over 14 years ago

0 replies • 29581 views
Discussion

Recovering "actionable" netlist from GDS II

Category: Custom IC Design

By GS202507021424

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started 1 hour ago

0 replies • 14 views
Discussion

Creating Assura DRC rule to check that sep of 2 layers is exactly 2 different values

Category: Custom IC Design

By Miguel V

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started 4 hours ago

0 replies • 24 views
Discussion

LVS Warning: “Unattached port label” for PLUS/MINUS on layer ind11_text — can’t locate device

Category: Custom IC Design

By RK202509013321

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updated 10 hours ago by RobMan

3 replies • 141 views
Discussion

PSS + PSTB for Buck converter

Category: Custom IC Design

By TH202510293247

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updated 11 hours ago by Frank Wiedmann

11 replies • 439 views
Discussion

Dual Core Oscillator Open Loop

Category: Custom IC Design

By IS20250922772

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started 12 hours ago

0 replies • 38 views
Discussion

Assembler: possible to disable automatic evaluation of output expressions?

Category: Custom IC Design

By dontpanic

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updated 23 hours ago by Andrew Beckett

1 replies • 135 views
Discussion

Assembler: possible to force inclusion of model file(s) at the very beginning of netlist?

Category: Custom IC Design

By dontpanic

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updated 23 hours ago by Andrew Beckett

3 replies • 326 views
Discussion

Interactive mode for Spectre using Python/TCL

Category: Custom IC Design

By CB202409064221

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updated 23 hours ago by Andrew Beckett

1 replies • 77 views
Discussion

Virtuoso AMS NOUNIT error with Xcelium - Not caching libraries

Category: Custom IC Design

By AS202502163432

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updated 1 day ago by Andrew Beckett

4 replies • 312 views
Discussion

Transfer design variable from schematic / layout to av_extracted view

Category: Custom IC Design

By FM202408077836

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started 1 day ago

0 replies • 51 views
Discussion

about cadence virtuoso guidance manual problem

Category: Custom IC Design

By JJ202503031042

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updated 1 day ago by Andrew Beckett

2 replies • 121 views
Discussion

PAC is giving 0V at the output

Category: Custom IC Design

By SA202512302438

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updated 1 day ago by Frank Wiedmann

2 replies • 181 views
Discussion

Query regarding Virtuoso EMX tool

Category: Custom IC Design

By VLSI lab IITB

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updated 4 days ago by Saloni Chhabra

3 replies • 236 views
Discussion

Replace symbol pin names without changing the pin placement and symbol boundary

Category: Custom IC Design

By SimhanAnalog

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updated 4 days ago by SimhanAnalog

4 replies • 640 views

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