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Custom IC Design

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  • Discussion

    probe a structure for all layout layers used in its build?

    Category: Custom IC Design

    By kenc184

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    updated over 3 years ago by kenc184

    5 replies • 9746 views
  • Discussion

    Layout XL : Connectivity - Update Function

    Category: Custom IC Design

    By amssshubham

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    updated over 3 years ago by Andrew Beckett

    4 replies • 6917 views
  • Discussion

    Cadence understand Poly resistor as a poly contact problem

    Category: Custom IC Design

    By Senan

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    updated over 3 years ago by Senan

    4 replies • 13769 views
  • Discussion

    When I open the simulation state which I create before, I can not reload the state and show the information below. What should I do to fix it?

    Category: Custom IC Design

    By SnowPine

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    updated over 3 years ago by Andrew Beckett

    6 replies • 12556 views
  • Discussion

    Create Label window disappears after selecting auto

    Category: Custom IC Design

    By delgsy

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    updated over 3 years ago by delgsy

    2 replies • 10536 views
  • Discussion

    Label created in an unknown layer

    Category: Custom IC Design

    By delgsy

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    •

    updated over 3 years ago by Andrew Beckett

    3 replies • 10101 views
  • Discussion

    Running Spectre simulation and then plotting in ViVA by using system() command from MATLAB

    Category: Custom IC Design

    By RFStuff

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    updated over 3 years ago by RFStuff

    6 replies • 11774 views
  • Discussion

    Changing names of multiple nets connected to a unique pin name

    Category: Custom IC Design

    By ud7842

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    updated over 3 years ago by Andrew Beckett

    3 replies • 12212 views
  • Discussion

    Clear/close a 'running' ADE-XL

    Category: Custom IC Design

    By TempViator

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    updated over 3 years ago by FormerMember

    7 replies • 5368 views
  • Discussion

    inductor LVS and netlisting

    Category: Custom IC Design

    By Karev11

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    •

    updated over 3 years ago by Andrew Beckett

    5 replies • 11692 views
  • Discussion

    Keysight ADS schematic into Virtuoso

    Category: Custom IC Design

    By sidm

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    updated over 3 years ago by sidm

    2 replies • 10496 views
  • Discussion

    Can Verilog-A macro names be swept in Corners Setup of ADE Assembler for Spectre simulations?

    Category: Custom IC Design

    By csn165309964

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    updated over 3 years ago by Andrew Beckett

    2 replies • 9670 views
  • Discussion

    Missing Corner Setups ADE Explorer

    Category: Custom IC Design

    By Kevin Buck

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    •

    updated over 3 years ago by Kevin Buck

    2 replies • 10228 views
  • Discussion

    Monte Carlo Simulation Results Canceled

    Category: Custom IC Design

    By ZpyIC123

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    •

    updated over 3 years ago by Andrew Beckett

    1 replies • 9056 views
  • Discussion

    Layers visibility issue in hierarchical layout design

    Category: Custom IC Design

    By Senan

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    •

    updated over 3 years ago by Senan

    2 replies • 9424 views
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