Custom IC Design

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Discussion

stb results different when iprobe placed at different location of the loop

Category: Custom IC Design

By a048

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updated 2 months ago by Frank Wiedmann

3 replies • 1189 views
Discussion

giolib045 "archaeology" (origin of giolib045.lib, giolib045.gds files)

Category: Custom IC Design

By GS202507021424

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started 2 months ago

0 replies • 323 views
Discussion

Schematic editor 2D array signal

Category: Custom IC Design

By kramnik

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updated 2 months ago by Andrew Beckett

1 replies • 856 views
Discussion

automate creration of calibre view from extraction for multiple extracted corners

Category: Custom IC Design

By micipici

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updated 2 months ago by Andrew Beckett

1 replies • 949 views
Discussion

Automatic routing using Cadence Virtuoso IC6.18.120

Category: Custom IC Design

By HN20250717689

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started 2 months ago

0 replies • 800 views
Discussion

How to greate guard ring for Cadence GPDK FinFet?

Category: Custom IC Design

By hesaliveJim

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updated 2 months ago by hesaliveJim

2 replies • 1053 views
Discussion

ADE ViVA Plotting Template: Where is it stored and how to edit?

Category: Custom IC Design

By StephanWeber

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updated 2 months ago by StephanWeber

2 replies • 1031 views
Discussion

How to load viaGetViaOptions Function inside PCELL

Category: Custom IC Design

By Esteban Saavedra

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updated 2 months ago by Andrew Beckett

4 replies • 1100 views
Discussion

Any analogue or mixed signal Cadence FinFet layouts to share?

Category: Custom IC Design

By hesaliveJim

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started 2 months ago

0 replies • 732 views
Discussion

verilog Syntax errors not highlighted in text editor

Category: Custom IC Design

By JavierC

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updated 2 months ago by JavierC

6 replies • 1651 views
Discussion

Loading *WARNING* Connection to MACHINE failed. Connection refused

Category: Custom IC Design

By hesaliveJim

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updated 2 months ago by hesaliveJim

4 replies • 1088 views
Discussion

Any major difference between Cadence Advanced Node GPDK v1.0 and v1.1 release?

Category: Custom IC Design

By hesaliveJim

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updated 2 months ago by hesaliveJim

1 replies • 886 views
Discussion

best way to integrate different calibre extraction corners to virtuoso ADE

Category: Custom IC Design

By micipici

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updated 2 months ago by Andrew Beckett

1 replies • 884 views
Discussion

Distributed simulations

Category: Custom IC Design

By OPump

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updated 2 months ago by OPump

1 replies • 848 views
Discussion

Automatic routing --> All nets in Layout GXL of Cadence Virtuoso

Category: Custom IC Design

By HN20250717689

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started 3 months ago

0 replies • 282 views

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