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Custom IC Design

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  • Discussion

    how to trim metal(overhangs over vias)

    Category: Custom IC Design

    By Nava5495

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    started over 3 years ago

    0 replies • 1240 views
  • Discussion

    How to change Default Decend View type

    Category: Custom IC Design

    By SpiceMonkey

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    updated over 3 years ago by SpiceMonkey

    6 replies • 12688 views
  • Discussion

    Pcells LVS fail. Master not found

    Category: Custom IC Design

    By RCardella

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    started over 3 years ago

    0 replies • 8558 views
  • Discussion

    Is there a quicker way to display an output after sims?

    Category: Custom IC Design

    By kenc184

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    updated over 3 years ago by kenc184

    3 replies • 9439 views
  • Discussion

    Verilog netlist wont explicit bit connected to bus pin

    Category: Custom IC Design

    By YB36

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    started over 3 years ago

    0 replies • 8860 views
  • Discussion

    How to get application type and/or window id from session

    Category: Custom IC Design

    By alexstepanov75

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    updated over 3 years ago by alexstepanov75

    5 replies • 3722 views
  • Discussion

    The way to define variable correlated to ac simulation in .scs model

    Category: Custom IC Design

    By sjwprcker

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    updated over 3 years ago by Andrew Beckett

    1 replies • 8809 views
  • Discussion

    maestro Results pane order. How to reset back to default?

    Category: Custom IC Design

    By Pirate King

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    updated over 3 years ago by Andrew Beckett

    2 replies • 10310 views
  • Discussion

    Performing Monte-Carlo simulation with AMS

    Category: Custom IC Design

    By Svilen64

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    updated over 3 years ago by FormerMember

    4 replies • 11305 views
  • Discussion

    Batch run simulations with different initial conditions.

    Category: Custom IC Design

    By skcy2001

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    updated over 3 years ago by FormerMember

    1 replies • 8787 views
  • Discussion

    Grouping instances in layout

    Category: Custom IC Design

    By Senan

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    updated over 3 years ago by Senan

    2 replies • 10083 views
  • Discussion

    Netlisting Unsuccessful for PEX Simulation in ADE/ADEXL

    Category: Custom IC Design

    By shbmsra12

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    updated over 3 years ago by shbmsra12

    4 replies • 8058 views
  • Discussion

    Segmentation fault upon VerilogA compilation with an if condition

    Category: Custom IC Design

    By AAbdelRahman

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    updated over 3 years ago by AAbdelRahman

    4 replies • 9974 views
  • Discussion

    Skill equivalent of "Open design in tab" in Assembler

    Category: Custom IC Design

    By alexstepanov75

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    updated over 3 years ago by alexstepanov75

    5 replies • 2294 views
  • Discussion

    How to assign two dimensional bus notation in schematics

    Category: Custom IC Design

    By delgsy

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    updated over 3 years ago by delgsy

    2 replies • 14067 views
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