Custom IC Design

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Discussion

name of nets inside deepprobe

Category: Custom IC Design

By Svilen64

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updated over 3 years ago by Svilen64

2 replies • 11003 views
Discussion

how to section comment in a DSPF file

Category: Custom IC Design

By Svilen64

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updated over 3 years ago by Svilen64

2 replies • 11598 views
Discussion

How to stop Ocean script from UINX

Category: Custom IC Design

By mgkang

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updated over 3 years ago by mgkang

2 replies • 9123 views
Discussion

schematic vs symbol pinorder.

Category: Custom IC Design

By kenc184

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updated over 3 years ago by kenc184

5 replies • 12463 views
Discussion

Can't get results from a PAC sim

Category: Custom IC Design

By forXTer

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updated over 3 years ago by Andrew Beckett

5 replies • 2886 views
Discussion

How to obtain Discrete-Time (DT) response from a switched-cap (SC) circuit (integrator)?

Category: Custom IC Design

By bernd2700

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updated over 3 years ago by Frank Wiedmann

52 replies • 34047 views
Discussion

Plot all digital traces in one subwindow

Category: Custom IC Design

By LuighiV

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updated over 3 years ago by Andrew Beckett

6 replies • 11751 views
Discussion

Assembler: possible to re-evaluate only results yielding "eval err" right after simulation?

Category: Custom IC Design

By dontpanic

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updated over 3 years ago by dontpanic

2 replies • 3722 views
Discussion

Maestro Expression Migration Problem

Category: Custom IC Design

By Kevin Buck

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updated over 3 years ago by Kevin Buck

3 replies • 9843 views
Discussion

how to update "design" when copy testbench

Category: Custom IC Design

By sjwprcker

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updated over 3 years ago by Andrew Beckett

1 replies • 1581 views
Discussion

Documentation about VNL netlist format

Category: Custom IC Design

By marcelpreda

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updated over 3 years ago by marcelpreda

2 replies • 8578 views
Discussion

Writing into a file in Verilog-A Model

Category: Custom IC Design

By Ketrin

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updated over 3 years ago by Ketrin

2 replies • 9301 views
Discussion

Sweep the real inductor value in virtuoso

Category: Custom IC Design

By Detailer

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updated over 3 years ago by Andrew Beckett

4 replies • 12109 views
Discussion

Could I run only one "runPlan" in Verifier?

Category: Custom IC Design

By SpiceMonkey

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updated over 3 years ago by Andrew Beckett

3 replies • 1776 views
Discussion

Pnoise analysis of a clock divider with uneven even/odd output cycles

Category: Custom IC Design

By csn165309964

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updated over 3 years ago by FormerMember

5 replies • 4328 views

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