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Digital Implementation

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  • Discussion

    CheckRoute

    Category: Digital Implementation

    By nidhin85 nidhin85

    •

    updated over 14 years ago by Vishnu Chada

    1 replies • 12822 views
  • Discussion

    Power Ring Via generation

    Category: Digital Implementation

    By bsdevlin bsdevlin

    •

    started over 14 years ago

    0 replies • 12728 views
  • Discussion

    issues with power routing

    Category: Digital Implementation

    By superman321 superman321

    •

    updated over 14 years ago by Kari

    21 replies • 20454 views
  • Discussion

    Encounter 8.1 vs 9.1 sdf generation

    Category: Digital Implementation

    By MzQuarter MzQuarter

    •

    updated over 14 years ago by MzQuarter

    8 replies • 17074 views
  • Discussion

    How can I go from gds to RC using Cadence QRC tool?

    Category: Digital Implementation

    By jpvSoccer jpvSoccer

    •

    started over 14 years ago

    0 replies • 12733 views
  • Discussion

    Gated flop count

    Category: Digital Implementation

    By kazad kazad

    •

    updated over 14 years ago by kazad

    6 replies • 15102 views
  • Discussion

    Comparing rho values in ict file with Design Rule Manual

    Category: Digital Implementation

    By Rajesh Vembu Rajesh Vembu

    •

    started over 14 years ago

    0 replies • 13025 views
  • Discussion

    cascade buffers on DontTouch nets during CTS

    Category: Digital Implementation

    By Rajesh Vembu Rajesh Vembu

    •

    updated over 14 years ago by Kari

    3 replies • 13371 views
  • Discussion

    Scan Reorder issue

    Category: Digital Implementation

    By Vishnu Chada Vishnu Chada

    •

    updated over 14 years ago by Vishnu Chada

    3 replies • 17115 views
  • Discussion

    Finding the leaf clock nets in the design

    Category: Digital Implementation

    By ssuhas ssuhas

    •

    updated over 14 years ago by Vishnu Chada

    4 replies • 15038 views
  • Discussion

    How to report list of flops whose clock port is driven by test clock in test mode

    Category: Digital Implementation

    By diablo diablo

    •

    updated over 14 years ago by diablo

    8 replies • 18991 views
  • Discussion

    Do Foundation Flows also exist for EPS or ETS?

    Category: Digital Implementation

    By pdgeek pdgeek

    •

    updated over 14 years ago by Kari

    2 replies • 13222 views
  • Discussion

    To avoid overlap of metals in different layers

    Category: Digital Implementation

    By surajece01 surajece01

    •

    updated over 14 years ago by Kari

    5 replies • 14280 views
  • Discussion

    EDI sdc read in error.

    Category: Digital Implementation

    By coffeelox coffeelox

    •

    updated over 14 years ago by coffeelox

    1 replies • 13543 views
  • Discussion

    checkSysConf on CentOS

    Category: Digital Implementation

    By cdnjr cdnjr

    •

    updated over 14 years ago by Kari

    1 replies • 13457 views
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