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Digital Implementation

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  • Discussion

    Genus Synthesis 15.2 vs 20.1

    Category: Digital Implementation

    By Azr

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    updated over 3 years ago by Azr

    2 replies • 9983 views
  • Discussion

    Netlist Power Analysis Flow with RTL Stimulus

    Category: Digital Implementation

    By dariomonti

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    updated over 3 years ago by mattiedaniels12

    5 replies • 11949 views
  • Discussion

    Creating power\ground pins for digital modules

    Category: Digital Implementation

    By Tom Urkin

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    •

    updated over 3 years ago by albertsilver

    4 replies • 7216 views
  • Discussion

    set_db cts_clustering_source_group_max_cloned_fraction 0.2

    Category: Digital Implementation

    By hammercui

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    updated over 3 years ago by william406

    3 replies • 11269 views
  • Discussion

    Correlated Corners

    Category: Digital Implementation

    By Ismat

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    started over 3 years ago

    0 replies • 8785 views
  • Discussion

    Understanding the exact definition of capacitances reported in the stdcells.report by Voltus in order to reuse for making power-domain decoupling models for EMC simulations

    Category: Digital Implementation

    By Herge

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    started over 3 years ago

    0 replies • 8231 views
  • Discussion

    How to keep specific Net Wires Spacing out with other net wires

    Category: Digital Implementation

    By ArcherGong

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    updated over 3 years ago by ArcherGong

    4 replies • 12325 views
  • Discussion

    [INNOVUS] Performing top level implementation for hierarchal/block IC design ("Bottom Up" approach)

    Category: Digital Implementation

    By TomBradyVLSI

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    updated over 3 years ago by henny123

    2 replies • 6152 views
  • Discussion

    Stylus flowtool

    Category: Digital Implementation

    By ccrumpnc

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    updated over 3 years ago by agelababypo

    6 replies • 23523 views
  • Discussion

    innovus saveNetlist issue (UPF_IS_1)

    Category: Digital Implementation

    By HappyHaHa

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    updated over 3 years ago by gavesit

    2 replies • 9871 views
  • Discussion

    report wire length in innovus timing report

    Category: Digital Implementation

    By cyll

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    •

    updated over 3 years ago by Andrew Beckett

    3 replies • 11059 views
  • Discussion

    route_special VDD VSS not interleaved.

    Category: Digital Implementation

    By Bentley

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    updated over 3 years ago by Bentley

    1 replies • 10988 views
  • Discussion

    MMMC cdB library in Voltus or Tempus 21.10

    Category: Digital Implementation

    By jeffreypr293

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    updated over 3 years ago by Hugdfig

    1 replies • 10123 views
  • Discussion

    [Innovus] create_generated_clock giving strange error TA-152

    Category: Digital Implementation

    By Nader Fathy

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    updated over 3 years ago by Nader Fathy

    9 replies • 15297 views
  • Discussion

    [Innovus] report the fanout of ICG

    Category: Digital Implementation

    By hammercui

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    updated over 3 years ago by hammercui

    6 replies • 14534 views
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