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Digital Implementation

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  • Discussion

    The viaGen found no shadow vias to rebuild

    Category: Digital Implementation

    By archive

    •

    updated over 18 years ago by Renee

    2 replies • 15122 views
  • Discussion

    Xilinx xc9500 and orcad 10.5

    Category: Digital Implementation

    By jyoung

    •

    started over 18 years ago

    0 replies • 14451 views
  • Discussion

    How to connect endcap cell vertically in soc encounter?

    Category: Digital Implementation

    By Renee

    •

    updated over 18 years ago by Kari

    10 replies • 19179 views
  • Discussion

    replace library cells

    Category: Digital Implementation

    By designer

    •

    updated over 18 years ago by designer

    2 replies • 15234 views
  • Discussion

    error after CTS: ERROR:TCLCMD-917

    Category: Digital Implementation

    By kulprashant

    •

    updated over 18 years ago by kulprashant

    10 replies • 7769 views
  • Discussion

    Why encounter places std cells on macro?

    Category: Digital Implementation

    By archive

    •

    updated over 18 years ago by ScreenName

    1 replies • 15026 views
  • Discussion

    How to set global clock signal routing in soc encounter?

    Category: Digital Implementation

    By Renee

    •

    updated over 18 years ago by Kari

    1 replies • 14962 views
  • Discussion

    senthesize sub-module

    Category: Digital Implementation

    By designer

    •

    started over 18 years ago

    0 replies • 14566 views
  • Discussion

    soc encounter output to Magic

    Category: Digital Implementation

    By Renee

    •

    updated over 18 years ago by Renee

    4 replies • 15692 views
  • Discussion

    First Encounter pin placement/layer

    Category: Digital Implementation

    By archive

    •

    updated over 18 years ago by Kari

    9 replies • 12337 views
  • Discussion

    Number of Non Equivalence Points after comparison in LEC Conformal

    Category: Digital Implementation

    By Azhar

    •

    updated over 18 years ago by Azhar

    1 replies • 17209 views
  • Discussion

    Encounter/Nanoroute - fixing DRC violations while keeping critical pre-routes untouched

    Category: Digital Implementation

    By ccabal

    •

    updated over 18 years ago by ccabal

    4 replies • 7597 views
  • Discussion

    Disable clock gating check for a module.

    Category: Digital Implementation

    By Tongju

    •

    started over 18 years ago

    0 replies • 18206 views
  • Discussion

    How to stream in Verilog to Virtuoso using "Retain reference library (No Merge)"

    Category: Digital Implementation

    By naderi

    •

    updated over 18 years ago by BobD

    3 replies • 3744 views
  • Discussion

    Power estimation after synthesis and Place-&-route

    Category: Digital Implementation

    By naderi

    •

    started over 18 years ago

    0 replies • 1108 views
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