Functional Verification

Latest Posts

Discussion

*E,OBJACC: Object must have write access: <object name>

Category: Functional Verification

By prkroon

$usertype
•
updated over 15 years ago by prkroon

4 replies • 6010 views
Discussion

What is the difference between E and Vera

Category: Functional Verification

By Raviram80

$usertype
•
updated over 15 years ago by teamspecman

2 replies • 15686 views
Discussion

Tracking signal values in simvision

Category: Functional Verification

By bgpradeep

$usertype
•
updated over 15 years ago by Tikesh

1 replies • 16803 views
Discussion

missing cdn_e_utility in vr_ahb (09.20.003-s )

Category: Functional Verification

By sunindew

$usertype
•
updated over 15 years ago by Mirit Fromovic

1 replies • 13711 views
Discussion

Event capture After Rerun in Specman

Category: Functional Verification

By JatinSavani

$usertype
•
started over 15 years ago

0 replies • 13426 views
Discussion

Specman Documentation Query

Category: Functional Verification

By Sarvesh

$usertype
•
updated over 15 years ago by swamiv

3 replies • 14558 views
Discussion

Vexp source causes Allegro to crash

Category: Functional Verification

By fmacc

$usertype
•
started over 15 years ago

0 replies • 13741 views
Discussion

Assertions

Category: Functional Verification

By Raviram80

$usertype
•
updated over 15 years ago by Raviram80

2 replies • 14442 views
Discussion

Stubs in E language

Category: Functional Verification

By Raviram80

$usertype
•
updated over 15 years ago by StephenH

2 replies • 14257 views
Discussion

Specman : check() and sys.finalize()

Category: Functional Verification

By Raviram80

$usertype
•
updated over 15 years ago by StephenH

1 replies • 14136 views
Discussion

BFM and Driver

Category: Functional Verification

By Raviram80

$usertype
•
updated over 15 years ago by StephenH

3 replies • 16711 views
Discussion

explenation on the verilog_wire() method

Category: Functional Verification

By archive

$usertype
•
updated over 15 years ago by sgor

2 replies • 14196 views
Discussion

System Verilog with Spice *F,INTERR - cu_check_port_var_aca

Category: Functional Verification

By GraemeNunn

$usertype
•
updated over 15 years ago by StephenH

1 replies • 1277 views
Discussion

Testbench with non-unique module names in sub-blocks

Category: Functional Verification

By mattyc

$usertype
•
updated over 15 years ago by StephenH

2 replies • 17953 views
Discussion

starting an executable from specman, how to ?

Category: Functional Verification

By archive

$usertype
•
updated over 15 years ago by archive

2 replies • 14067 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.