Functional Verification

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Discussion

Xcelium: Altering return value of $temperature in digital simulation

Category: Functional Verification

By MartinJ
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updated over 5 years ago by MartinJ

2 replies • 15285 views
Discussion

fatal voltage source/inductor loop

Category: Functional Verification

By Ben321
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started over 5 years ago

0 replies • 2565 views
Discussion

vAPI filter return no duplciate

Category: Functional Verification

By yPerrot
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updated over 5 years ago by yPerrot

2 replies • 14278 views
Discussion

SystemVerilog EEnet input driven by current source

Category: Functional Verification

By HoWei
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started over 5 years ago

0 replies • 14787 views
Discussion

Instantiate SystemC module in SystemVerilog module with real/double ports

Category: Functional Verification

By coderoo
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started over 5 years ago

0 replies • 4173 views
Discussion

e code coverage

Category: Functional Verification

By aefody
•
updated over 5 years ago by aefody

2 replies • 14739 views
Discussion

Analog circuit designing

Category: Functional Verification

By Meer
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started over 5 years ago

0 replies • 13453 views
Discussion

[JasperGold] Behavioral Analysis - How to exercise it properly?

Category: Functional Verification

By Murilo Santos
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started over 5 years ago

0 replies • 1373 views
Discussion

generate over a loop the same module with different parameter and maintain it in systemverilog UVM environment

Category: Functional Verification

By EranW
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updated over 5 years ago by EranW

2 replies • 13602 views
Discussion

Does driver trace through system verilog interfaces ever work?

Category: Functional Verification

By ese002b
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updated over 5 years ago by ese002b

2 replies • 15317 views
Discussion

Lint errors

Category: Functional Verification

By parvathyram
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started over 5 years ago

0 replies • 13314 views
Discussion

irun & ncvlog version conflict

Category: Functional Verification

By Zdeno
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updated over 5 years ago by Zdeno

3 replies • 7137 views
Discussion

Excluding unused functions in JasperGold Superlint

Category: Functional Verification

By Max Bjurling
•
started over 5 years ago

0 replies • 13818 views
Discussion

How do we extract a full path design from Scoreboard when there is a `uvm_error?

Category: Functional Verification

By EranW
•
updated over 5 years ago by StephenH

3 replies • 16265 views
Discussion

Add a button to specview?

Category: Functional Verification

By aefody
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updated over 5 years ago by hannes

3 replies • 15365 views

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