Functional Verification

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Discussion

How do I add signal probes to Simvision waveform viewer?

Category: Functional Verification

By ianmurph

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updated over 2 years ago by StephenH

19 replies • 26747 views
Discussion

What is Xcelium's equivalent of VCS's deraceclockdata option?

Category: Functional Verification

By Vijayvithal

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updated over 2 years ago by StephenH

3 replies • 5355 views
Discussion

Xcelium simulator is not running when vhpi application is loaded.

Category: Functional Verification

By John Davis

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updated over 2 years ago by John Davis

9 replies • 11624 views
Discussion

vManager Error "Failed to send chunk"

Category: Functional Verification

By omerp852

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updated over 2 years ago by StephenH

1 replies • 1638 views
Discussion

MISE(Multi-Snapshot Incremental Elaboration)with Gate level files

Category: Functional Verification

By meowww

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updated over 2 years ago by StephenH

1 replies • 2712 views
Discussion

why my xrun does not compile UVM library package automatically？

Category: Functional Verification

By galenxiao

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updated over 2 years ago by StephenH

1 replies • 10707 views
Discussion

Xcelium 21.09 Installation setting and manual(?)

Category: Functional Verification

By zhliang

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updated over 2 years ago by zhliang

5 replies • 30134 views
Discussion

Xprop reset setting in tcl

Category: Functional Verification

By smseok

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started over 2 years ago

0 replies • 6767 views
Discussion

Error : lps_1801 elaboration : *E,MTOMDU : More than one unit matches 'TESTBENCH'

Category: Functional Verification

By Zero00

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updated over 2 years ago by Zero00

6 replies • 5371 views
Discussion

Windows/ Mac compatibility for Cadence softwares

Category: Functional Verification

By asiddharthrao

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updated over 2 years ago by StephenH

1 replies • 13231 views
Discussion

xcellium compiles every RTL hierarchy into a "library_cell", how do I get rid of that?

Category: Functional Verification

By mxlusereight

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updated over 2 years ago by mxlusereight

2 replies • 2163 views
Discussion

simvision

Category: Functional Verification

By schetan

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started over 2 years ago

0 replies • 6937 views
Discussion

<EE> ERROR: VRsrc instance behavioral_modelling_doubler_full.I26.S0o node P unconverged at T=125005ns

Category: Functional Verification

By swethasam

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started over 2 years ago

0 replies • 660 views
Discussion

unable to simulate VHDL record constant assignment through component port

Category: Functional Verification

By Hunen

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updated over 2 years ago by tpylant

3 replies • 8363 views
Discussion

Can queues be used to drive RTL?

Category: Functional Verification

By shareefj

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updated over 2 years ago by shareefj

5 replies • 8567 views

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