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Functional Verification

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  • Discussion

    Free version of NC-Verilog

    Category: Functional Verification

    By Daniel Figueiredo

    •

    updated over 3 years ago by StephenH

    3 replies • 10669 views
  • Discussion

    Irun error MXINDR with a verilog PLL model wrapper written in VHDL, any way to workaround?

    Category: Functional Verification

    By mxlusereight

    •

    updated over 3 years ago by mxlusereight

    2 replies • 8677 views
  • Discussion

    How to Map covergroup from present regression database to a reference vPlan

    Category: Functional Verification

    By Rolly

    •

    updated over 3 years ago by StephenH

    1 replies • 8749 views
  • Discussion

    Xcelium waveform dump into custom directory

    Category: Functional Verification

    By DamianRRR

    •

    updated over 3 years ago by StephenH

    1 replies • 11494 views
  • Discussion

    System Verilog: always @( * ) is not working, but explicit declaration always @( s1, s1, s3) is working

    Category: Functional Verification

    By HoWei

    •

    updated over 3 years ago by HoWei

    5 replies • 16412 views
  • Discussion

    Jaspergold -- Net does not have a driver

    Category: Functional Verification

    By Vivek Kakkireni

    •

    updated over 3 years ago by ErikSeligman

    1 replies • 3312 views
  • Discussion

    How do I add signal probes to Simvision waveform viewer?

    Category: Functional Verification

    By ianmurph

    •

    updated over 3 years ago by StephenH

    19 replies • 32800 views
  • Discussion

    What is Xcelium's equivalent of VCS's deraceclockdata option?

    Category: Functional Verification

    By Vijayvithal

    •

    updated over 3 years ago by StephenH

    3 replies • 6635 views
  • Discussion

    Xcelium simulator is not running when vhpi application is loaded.

    Category: Functional Verification

    By John Davis

    •

    updated over 3 years ago by John Davis

    9 replies • 14302 views
  • Discussion

    vManager Error "Failed to send chunk"

    Category: Functional Verification

    By omerp852

    •

    updated over 3 years ago by StephenH

    1 replies • 1943 views
  • Discussion

    MISE(Multi-Snapshot Incremental Elaboration)with Gate level files

    Category: Functional Verification

    By meowww

    •

    updated over 3 years ago by StephenH

    1 replies • 3284 views
  • Discussion

    why my xrun does not compile UVM library package automatically?

    Category: Functional Verification

    By galenxiao

    •

    updated over 3 years ago by StephenH

    1 replies • 12899 views
  • Discussion

    Xcelium 21.09 Installation setting and manual(?)

    Category: Functional Verification

    By zhliang

    •

    updated over 3 years ago by zhliang

    5 replies • 35827 views
  • Discussion

    Xprop reset setting in tcl

    Category: Functional Verification

    By smseok

    •

    started over 3 years ago

    0 replies • 7943 views
  • Discussion

    Error : lps_1801 elaboration : *E,MTOMDU : More than one unit matches 'TESTBENCH'

    Category: Functional Verification

    By Zero00

    •

    updated over 3 years ago by Zero00

    6 replies • 6677 views
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