Logic Design

Latest Posts

Discussion

In Simvision, how do I change the waveform font size of the signal names?

Category: Logic Design

By mxlusereight
•
started over 2 years ago

0 replies • 7873 views
Discussion

read from text file with two values and represent that as voltage signals on two different port a and b

Category: Logic Design

By Hagar Hendy
•
updated over 2 years ago by ShawnLogan

1 replies • 7048 views
Discussion

Constraining some nets to route through a specific metal layer, and changing some pin/cell placements and wire directions in Cadence Innovus.

Category: Logic Design

By Riya C
•
updated over 2 years ago by Riya C

2 replies • 8158 views
Discussion

Digital Custom Placer Via not placing

Category: Logic Design

By KhanAmir
•
updated over 2 years ago by realakirabutt

3 replies • 7937 views
Discussion

Instance of standard cell does not have layout?

Category: Logic Design

By KhanAmir
•
updated over 2 years ago by DimoM

3 replies • 9653 views
Discussion

HELP WITH Integral nonlinearity (INL) and differential nonlinearity (DNL) of data converters

Category: Logic Design

By Saori
•
updated over 2 years ago by ShawnLogan

1 replies • 8202 views
Discussion

End cap/boundary cell in my pdk from LFoundary

Category: Logic Design

By KhanAmir
•
updated over 2 years ago by KhanAmir

6 replies • 4081 views
Discussion

Decoder standalone synthesis in Genus

Category: Logic Design

By KhanAmir
•
started over 2 years ago

0 replies • 7963 views
Discussion

Cadence Encounter and Innovus Library Compatibility.

Category: Logic Design

By Riya C
•
updated over 2 years ago by Riya C

4 replies • 10950 views
Discussion

cadence Digital design

Category: Logic Design

By blossom
•
updated over 2 years ago by MTYM

1 replies • 10138 views
Discussion

when i use the elc, i found these problems, please help me!

Category: Logic Design

By WANGZHELONG
•
started over 2 years ago

0 replies • 8456 views
Discussion

Genus Synthesis not preserving register for sequential logic with pragma.

Category: Logic Design

By RichaV
•
started over 3 years ago

0 replies • 9917 views
Discussion

Can we do synthesis by using variables in generate block

Category: Logic Design

By RFStuff
•
started over 3 years ago

0 replies • 9232 views
Discussion

Reading data from a file and assign those into a parametric array in verilogAMS

Category: Logic Design

By RFStuff
•
updated over 3 years ago by Andrew Beckett

4 replies • 12085 views
Discussion

RTL Design of SPI

Category: Logic Design

By swe
•
started over 3 years ago

0 replies • 9845 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.