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Logic Design

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  • Discussion

    RTL vs. gate netlist verification mapping problem

    Category: Logic Design

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    started over 17 years ago

    0 replies • 13532 views
  • Discussion

    Gate-leve sim, sdf back annotation warnings

    Category: Logic Design

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    started over 17 years ago

    0 replies • 15129 views
  • Discussion

    reporting gate count

    Category: Logic Design

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    updated over 17 years ago by archive

    2 replies • 17771 views
  • Discussion

    Can we read extracted timing model in RC

    Category: Logic Design

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    updated over 17 years ago by archive

    1 replies • 14113 views
  • Discussion

    RTL vs. gate netlist verification mapping problem

    Category: Logic Design

    By archive

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    •

    updated over 17 years ago by archive

    1 replies • 14556 views
  • Discussion

    Unmapped point (extra)

    Category: Logic Design

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    updated over 17 years ago by archive

    1 replies • 14683 views
  • Discussion

    inverted equivalent points

    Category: Logic Design

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    updated over 17 years ago by archive

    1 replies • 17321 views
  • Discussion

    help needed

    Category: Logic Design

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    updated over 17 years ago by archive

    1 replies • 13795 views
  • Discussion

    Non-equivalences due to different device.

    Category: Logic Design

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    updated over 17 years ago by archive

    1 replies • 13738 views
  • Discussion

    ncelab: *W,BIGWBS

    Category: Logic Design

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    updated over 17 years ago by archive

    4 replies • 3821 views
  • Discussion

    Gate-leve sim, sdf back annotation warnings

    Category: Logic Design

    By archive

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    updated over 17 years ago by archive

    2 replies • 21090 views
  • Discussion

    flattening synthetic operators

    Category: Logic Design

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    updated over 17 years ago by archive

    2 replies • 14372 views
  • Discussion

    sub architecture selection

    Category: Logic Design

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    updated over 17 years ago by archive

    13 replies • 21148 views
  • Discussion

    Using Ocean scripts to calculate simulation data.

    Category: Logic Design

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    updated over 17 years ago by archive

    3 replies • 14417 views
  • Discussion

    Unmapped point (not-mapped) issue

    Category: Logic Design

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    updated over 17 years ago by archive

    3 replies • 17586 views
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