Logic Design

Latest Posts

Discussion

RTL vs. gate netlist verification mapping problem

Category: Logic Design

By admin
•
started over 17 years ago

0 replies • 12771 views
Discussion

Gate-leve sim, sdf back annotation warnings

Category: Logic Design

By admin
•
started over 17 years ago

0 replies • 14319 views
Discussion

reporting gate count

Category: Logic Design

By archive
•
updated over 17 years ago by archive

2 replies • 16649 views
Discussion

Can we read extracted timing model in RC

Category: Logic Design

By archive
•
updated over 17 years ago by archive

1 replies • 13290 views
Discussion

RTL vs. gate netlist verification mapping problem

Category: Logic Design

By archive
•
updated over 17 years ago by archive

1 replies • 13658 views
Discussion

Unmapped point (extra)

Category: Logic Design

By archive
•
updated over 17 years ago by archive

1 replies • 13749 views
Discussion

inverted equivalent points

Category: Logic Design

By archive
•
updated over 17 years ago by archive

1 replies • 16242 views
Discussion

help needed

Category: Logic Design

By archive
•
updated over 17 years ago by archive

1 replies • 12980 views
Discussion

Non-equivalences due to different device.

Category: Logic Design

By archive
•
updated over 17 years ago by archive

1 replies • 12935 views
Discussion

ncelab: *W,BIGWBS

Category: Logic Design

By archive
•
updated over 17 years ago by archive

4 replies • 3384 views
Discussion

Gate-leve sim, sdf back annotation warnings

Category: Logic Design

By archive
•
updated over 17 years ago by archive

2 replies • 19810 views
Discussion

flattening synthetic operators

Category: Logic Design

By archive
•
updated over 17 years ago by archive

2 replies • 13459 views
Discussion

sub architecture selection

Category: Logic Design

By archive
•
updated over 17 years ago by archive

13 replies • 19150 views
Discussion

Using Ocean scripts to calculate simulation data.

Category: Logic Design

By archive
•
updated over 17 years ago by archive

3 replies • 13492 views
Discussion

Unmapped point (not-mapped) issue

Category: Logic Design

By archive
•
updated over 17 years ago by archive

3 replies • 16273 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.