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Logic Design

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  • Discussion

    Getting Warning X library error detected while trying to open gui for CCD

    Category: Logic Design

    By rgaddh rgaddh

    •

    updated over 15 years ago by croy

    1 replies • 13613 views
  • Discussion

    How do I count that how mant parts are in the library?

    Category: Logic Design

    By Jennie Jennie

    •

    updated over 15 years ago by Jennie

    1 replies • 13206 views
  • Discussion

    Heterogeneous and homogeneous library part issue

    Category: Logic Design

    By Jennie Jennie

    •

    updated over 15 years ago by Jennie

    1 replies • 14283 views
  • Discussion

    Increasing the Simulation Step Time for 1 ns..?

    Category: Logic Design

    By Sunil Kumar K Sunil Kumar K

    •

    updated over 15 years ago by Abha

    1 replies • 13183 views
  • Discussion

    ungrouping certain hierarchies (RTLC loop issue)

    Category: Logic Design

    By Kamal Kundu Kamal Kundu

    •

    updated over 15 years ago by grasshopper

    1 replies • 15315 views
  • Discussion

    report_case_analysis in RTL Compiler

    Category: Logic Design

    By Kamal Kundu Kamal Kundu

    •

    updated over 15 years ago by grasshopper

    1 replies • 13263 views
  • Discussion

    Properties editor display format

    Category: Logic Design

    By Jennie Jennie

    •

    updated over 15 years ago by Jennie

    2 replies • 13346 views
  • Discussion

    2nd TIP OF THE MONTH : Beware Incomplete Libraries

    Category: Logic Design

    By archive archive

    •

    updated over 15 years ago by croy

    2 replies • 13089 views
  • Discussion

    altium sch. to allegro

    Category: Logic Design

    By jpacd1x jpacd1x

    •

    started over 15 years ago

    0 replies • 12665 views
  • Discussion

    RTL design

    Category: Logic Design

    By JLKL JLKL

    •

    started over 15 years ago

    0 replies • 12733 views
  • Discussion

    Square Wave oscillator output error

    Category: Logic Design

    By Electriconic Electriconic

    •

    updated over 15 years ago by acnetreatment

    2 replies • 13687 views
  • Discussion

    verilog . D-latch with memory.

    Category: Logic Design

    By dvdeepak dvdeepak

    •

    updated over 15 years ago by dvdeepak

    2 replies • 15767 views
  • Discussion

    Complier error

    Category: Logic Design

    By jahanzebanwer jahanzebanwer

    •

    updated over 15 years ago by tpylant

    1 replies • 12981 views
  • Discussion

    cds_thru woes in Diva LVS and DRC

    Category: Logic Design

    By asd1815 asd1815

    •

    started over 15 years ago

    0 replies • 13059 views
  • Discussion

    RTL compiler - eleborate issue.

    Category: Logic Design

    By sandeepsuhas sandeepsuhas

    •

    updated over 15 years ago by mclarke

    1 replies • 2832 views
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