Logic Design

Latest Posts

Discussion

lec nonequivalent on bi-di IO Pad

Category: Logic Design

By Arcade9999
•
started over 15 years ago

0 replies • 13105 views
Discussion

LEC between a posedge DFF and a low-pass D latch followed by a posedge D flop

Category: Logic Design

By WorldMaker
•
updated over 15 years ago by WorldMaker

1 replies • 13928 views
Discussion

memory LEC

Category: Logic Design

By WorldMaker
•
updated over 15 years ago by WorldMaker

2 replies • 13405 views
Discussion

Encounter Write_sdf generate error with Modelsim

Category: Logic Design

By rv01
•
updated over 15 years ago by TAM1

1 replies • 15004 views
Discussion

Part-table and bodies versions

Category: Logic Design

By DominiqueP
•
started over 15 years ago

0 replies • 12660 views
Discussion

Help: memory equivalence check between RTL and schematic

Category: Logic Design

By WorldMaker
•
updated over 15 years ago by archive

3 replies • 14553 views
Discussion

lec blackbox nonequivalent problem

Category: Logic Design

By Arcade9999
•
updated over 15 years ago by croy

1 replies • 15440 views
Discussion

constraint file

Category: Logic Design

By my screen
•
updated over 15 years ago by grasshopper

1 replies • 15947 views
Discussion

Ideal Diode Model?

Category: Logic Design

By romanjcg
•
updated over 15 years ago by oldmouldy

1 replies • 15263 views
Discussion

Simulation of file .JED

Category: Logic Design

By adios
•
updated over 15 years ago by adios

2 replies • 13773 views
Discussion

Constraint two path in the design to have equal propagation delay

Category: Logic Design

By diablo
•
updated over 15 years ago by Genky

3 replies • 14079 views
Discussion

Synthesize problem

Category: Logic Design

By Hava
•
updated over 15 years ago by tiasmith123

3 replies • 13866 views
Discussion

Viewing a .SCH file

Category: Logic Design

By Aule Mar
•
updated over 15 years ago by oldmouldy

1 replies • 14801 views
Discussion

Need help with VHDL libraries in RTL Compiler

Category: Logic Design

By yqzhang
•
updated over 15 years ago by Mickey

1 replies • 14217 views
Discussion

User defined data registers in JTAG

Category: Logic Design

By Leo1008
•
updated over 15 years ago by ahnnelopez

2 replies • 13986 views

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