Logic Design

Latest Posts

Discussion

RTL design

Category: Logic Design

By JLKL
•
started over 16 years ago

0 replies • 14482 views
Discussion

Square Wave oscillator output error

Category: Logic Design

By Electriconic
•
updated over 16 years ago by acnetreatment

2 replies • 16150 views
Discussion

verilog . D-latch with memory.

Category: Logic Design

By dvdeepak
•
updated over 16 years ago by dvdeepak

2 replies • 18006 views
Discussion

Complier error

Category: Logic Design

By jahanzebanwer
•
updated over 16 years ago by tpylant

1 replies • 14837 views
Discussion

cds_thru woes in Diva LVS and DRC

Category: Logic Design

By asd1815
•
started over 16 years ago

0 replies • 14824 views
Discussion

RTL compiler - eleborate issue.

Category: Logic Design

By sandeepsuhas
•
updated over 16 years ago by mclarke

1 replies • 3626 views
Discussion

lec nonequivalent on bi-di IO Pad

Category: Logic Design

By Arcade9999
•
started over 16 years ago

0 replies • 14879 views
Discussion

LEC between a posedge DFF and a low-pass D latch followed by a posedge D flop

Category: Logic Design

By WorldMaker
•
updated over 16 years ago by WorldMaker

1 replies • 16089 views
Discussion

memory LEC

Category: Logic Design

By WorldMaker
•
updated over 16 years ago by WorldMaker

2 replies • 15475 views
Discussion

Encounter Write_sdf generate error with Modelsim

Category: Logic Design

By rv01
•
updated over 16 years ago by TAM1

1 replies • 17191 views
Discussion

Part-table and bodies versions

Category: Logic Design

By DominiqueP
•
started over 16 years ago

0 replies • 14317 views
Discussion

Help: memory equivalence check between RTL and schematic

Category: Logic Design

By WorldMaker
•
updated over 16 years ago by archive

3 replies • 17216 views
Discussion

lec blackbox nonequivalent problem

Category: Logic Design

By Arcade9999
•
updated over 16 years ago by croy

1 replies • 17847 views
Discussion

constraint file

Category: Logic Design

By my screen
•
updated over 16 years ago by grasshopper

1 replies • 18670 views
Discussion

Ideal Diode Model?

Category: Logic Design

By romanjcg
•
updated over 16 years ago by oldmouldy

1 replies • 17495 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.