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Logic Design

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  • Discussion

    verilog . D-latch with memory.

    Category: Logic Design

    By dvdeepak

    •

    updated over 16 years ago by dvdeepak

    2 replies • 17899 views
  • Discussion

    Complier error

    Category: Logic Design

    By jahanzebanwer

    •

    updated over 16 years ago by tpylant

    1 replies • 14788 views
  • Discussion

    cds_thru woes in Diva LVS and DRC

    Category: Logic Design

    By asd1815

    •

    started over 16 years ago

    0 replies • 14785 views
  • Discussion

    RTL compiler - eleborate issue.

    Category: Logic Design

    By sandeepsuhas

    •

    updated over 16 years ago by mclarke

    1 replies • 3568 views
  • Discussion

    lec nonequivalent on bi-di IO Pad

    Category: Logic Design

    By Arcade9999

    •

    started over 16 years ago

    0 replies • 14835 views
  • Discussion

    LEC between a posedge DFF and a low-pass D latch followed by a posedge D flop

    Category: Logic Design

    By WorldMaker

    •

    updated over 16 years ago by WorldMaker

    1 replies • 16001 views
  • Discussion

    memory LEC

    Category: Logic Design

    By WorldMaker

    •

    updated over 16 years ago by WorldMaker

    2 replies • 15399 views
  • Discussion

    Encounter Write_sdf generate error with Modelsim

    Category: Logic Design

    By rv01

    •

    updated over 16 years ago by TAM1

    1 replies • 17112 views
  • Discussion

    Part-table and bodies versions

    Category: Logic Design

    By DominiqueP

    •

    started over 16 years ago

    0 replies • 14288 views
  • Discussion

    Help: memory equivalence check between RTL and schematic

    Category: Logic Design

    By WorldMaker

    •

    updated over 16 years ago by archive

    3 replies • 17074 views
  • Discussion

    lec blackbox nonequivalent problem

    Category: Logic Design

    By Arcade9999

    •

    updated over 16 years ago by croy

    1 replies • 17749 views
  • Discussion

    constraint file

    Category: Logic Design

    By my screen

    •

    updated over 16 years ago by grasshopper

    1 replies • 18572 views
  • Discussion

    Ideal Diode Model?

    Category: Logic Design

    By romanjcg

    •

    updated over 16 years ago by oldmouldy

    1 replies • 17418 views
  • Discussion

    Simulation of file .JED

    Category: Logic Design

    By adios

    •

    updated over 16 years ago by adios

    2 replies • 15760 views
  • Discussion

    Constraint two path in the design to have equal propagation delay

    Category: Logic Design

    By diablo

    •

    updated over 16 years ago by Genky

    3 replies • 16333 views
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