• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Logic Design
CDNS - double leaderboard script

Logic Design

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Latest Posts

  • Create a new Post
  • Discussion

    Synthesize problem

    Category: Logic Design

    By Hava

    •

    updated over 16 years ago by tiasmith123

    3 replies • 15983 views
  • Discussion

    Viewing a .SCH file

    Category: Logic Design

    By Aule Mar

    •

    updated over 16 years ago by oldmouldy

    1 replies • 16956 views
  • Discussion

    Need help with VHDL libraries in RTL Compiler

    Category: Logic Design

    By yqzhang

    •

    updated over 16 years ago by Mickey

    1 replies • 16064 views
  • Discussion

    User defined data registers in JTAG

    Category: Logic Design

    By Leo1008

    •

    updated over 16 years ago by ahnnelopez

    2 replies • 16057 views
  • Discussion

    naming style for generate statement in RTL

    Category: Logic Design

    By diablo

    •

    updated over 16 years ago by angelster

    5 replies • 19676 views
  • Discussion

    error occured while importing netlist

    Category: Logic Design

    By gopinathkannan

    •

    updated over 16 years ago by ryangarg05

    4 replies • 16055 views
  • Discussion

    how to prevent the use of specific library cells for some instance in the design?

    Category: Logic Design

    By diablo

    •

    updated over 16 years ago by dacyace24

    4 replies • 16537 views
  • Discussion

    Does anyone have the 0.18um standard cell library?

    Category: Logic Design

    By learnlearn1

    •

    updated over 16 years ago by jflieder

    1 replies • 14873 views
  • Discussion

    Customer Support Solution 11014718

    Category: Logic Design

    By stump1019

    •

    updated over 16 years ago by redwire

    1 replies • 14727 views
  • Discussion

    TAP Control signals

    Category: Logic Design

    By Leo1008

    •

    updated over 16 years ago by Andy Hughes

    1 replies • 15267 views
  • Discussion

    Propagated clocks

    Category: Logic Design

    By gchalive

    •

    updated over 16 years ago by grasshopper

    3 replies • 20315 views
  • Discussion

    Verilog Netlist to VHDL Netlist?

    Category: Logic Design

    By Scrivner

    •

    updated over 16 years ago by TAM1

    1 replies • 15768 views
  • Discussion

    Upcoming Conformal Products 9.1 Release

    Category: Logic Design

    By petrak

    •

    started over 16 years ago

    0 replies • 14218 views
  • Discussion

    Specifying timing path for synchronous circuits

    Category: Logic Design

    By gchalive

    •

    updated over 16 years ago by gchalive

    6 replies • 18452 views
  • Discussion

    STA in RC

    Category: Logic Design

    By gchalive

    •

    updated over 16 years ago by grasshopper

    3 replies • 15772 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information