Logic Design

Latest Posts

Discussion

naming style for generate statement in RTL

Category: Logic Design

By diablo
•
updated over 15 years ago by angelster

5 replies • 16970 views
Discussion

error occured while importing netlist

Category: Logic Design

By gopinathkannan
•
updated over 15 years ago by ryangarg05

4 replies • 13938 views
Discussion

how to prevent the use of specific library cells for some instance in the design?

Category: Logic Design

By diablo
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updated over 15 years ago by dacyace24

4 replies • 14241 views
Discussion

Does anyone have the 0.18um standard cell library?

Category: Logic Design

By learnlearn1
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updated over 15 years ago by jflieder

1 replies • 13050 views
Discussion

Customer Support Solution 11014718

Category: Logic Design

By stump1019
•
updated over 15 years ago by redwire

1 replies • 12977 views
Discussion

TAP Control signals

Category: Logic Design

By Leo1008
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updated over 15 years ago by Andy Hughes

1 replies • 13299 views
Discussion

Propagated clocks

Category: Logic Design

By gchalive
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updated over 15 years ago by grasshopper

3 replies • 17298 views
Discussion

Verilog Netlist to VHDL Netlist?

Category: Logic Design

By Scrivner
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updated over 15 years ago by TAM1

1 replies • 13790 views
Discussion

Upcoming Conformal Products 9.1 Release

Category: Logic Design

By petrak
•
started over 15 years ago

0 replies • 12556 views
Discussion

Specifying timing path for synchronous circuits

Category: Logic Design

By gchalive
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updated over 15 years ago by gchalive

6 replies • 15516 views
Discussion

STA in RC

Category: Logic Design

By gchalive
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updated over 15 years ago by grasshopper

3 replies • 13704 views
Discussion

CadenceRC area report

Category: Logic Design

By Hava
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updated over 15 years ago by Hava

6 replies • 17662 views
Discussion

Synthesizing Mixed Verilog-VHDL in RTL Compiler?

Category: Logic Design

By Scrivner
•
updated over 15 years ago by Scrivner

2 replies • 15061 views
Discussion

In encounter RTL compiler, how can I apply speed or size optimization options

Category: Logic Design

By learnlearn1
•
updated over 15 years ago by learnlearn1

2 replies • 13273 views
Discussion

How do I connect an instiantiated library clock gating cell to scan chains?

Category: Logic Design

By maxb
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updated over 16 years ago by Henry Wang

1 replies • 14585 views

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