Logic Design

Latest Posts

Discussion

Unit names for vhdl and verilog

Category: Logic Design

By ras thomas

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updated over 16 years ago by ras thomas

1 replies • 14259 views
Discussion

why IUS so sloooooow ?

Category: Logic Design

By duckfly

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updated over 16 years ago by Adam Sherer

4 replies • 1521 views
Discussion

Power nets vs offpage connector

Category: Logic Design

By Jamez

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updated over 16 years ago by oldmouldy

1 replies • 14715 views
Discussion

ETS software crash

Category: Logic Design

By MarceloLucena

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updated over 16 years ago by MarceloLucena

1 replies • 13667 views
Discussion

Problems Saving in .SCH format

Category: Logic Design

By xmoix

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updated over 16 years ago by oldmouldy

1 replies • 13834 views
Discussion

license error on my system

Category: Logic Design

By havisingh

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updated over 16 years ago by havisingh

2 replies • 16166 views
Discussion

No binary/Encrypted TCL(tcl compiler) support in all cadence tools, but Yes in Synopsys!

Category: Logic Design

By iceda

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updated over 16 years ago by grasshopper

5 replies • 4368 views
Discussion

LEC Issue with falling edge clock gater cells

Category: Logic Design

By FredS

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updated over 16 years ago by croy

1 replies • 14207 views
Discussion

Overwriting messages warning in RC

Category: Logic Design

By shift

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updated over 16 years ago by shift

2 replies • 14172 views
Discussion

choosing a decision between buffer and inverter in CTS

Category: Logic Design

By mmkrcool

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started over 16 years ago

0 replies • 13787 views
Discussion

Layout

Category: Logic Design

By Hoda

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updated over 16 years ago by johannes

1 replies • 13530 views
Discussion

How to increase timing table dimensions in a lib file created from do_extract_model

Category: Logic Design

By vavendan

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updated over 16 years ago by johannes

1 replies • 13774 views
Discussion

Path _Delay Command

Category: Logic Design

By Kliatakis

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updated over 16 years ago by Kliatakis

2 replies • 1176 views
Discussion

Routing info in Encounter

Category: Logic Design

By Calistudent

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updated over 16 years ago by johannes

1 replies • 13557 views
Discussion

Cadence 6.1.3 libraries

Category: Logic Design

By StreamCX

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updated over 16 years ago by archive

3 replies • 10572 views

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