Logic Design

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Discussion

Cadence 6.1.3 libraries

Category: Logic Design

By StreamCX

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updated over 16 years ago by archive

3 replies • 10732 views
Discussion

Hspice Monte Carlo .measure statement use.

Category: Logic Design

By pjparekh

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started over 16 years ago

0 replies • 17721 views
Discussion

SOC Encounter

Category: Logic Design

By Oysters

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updated over 16 years ago by gops

3 replies • 15805 views
Discussion

annotating switching activity

Category: Logic Design

By alexsieh

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updated over 17 years ago by alexsieh

7 replies • 18974 views
Discussion

synopsys designware can not be compiled in the conformal Equivalence

Category: Logic Design

By misspark

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updated over 17 years ago by tstark

1 replies • 16754 views
Discussion

can LEC provide cdc check?

Category: Logic Design

By zhiweiwu0318

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updated over 17 years ago by timmynolan

9 replies • 19699 views
Discussion

Op- Amp loop gain measurement

Category: Logic Design

By Saran84

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updated over 17 years ago by johannes

1 replies • 1578 views
Discussion

Wish you Happy New Year.

Category: Logic Design

By Raam

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started over 17 years ago

0 replies • 13752 views
Discussion

RTL Compiler: is there a timing path between 2 FF?

Category: Logic Design

By magic

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updated over 17 years ago by magic

3 replies • 14762 views
Discussion

How to save global constrain settings In Allegro?

Category: Logic Design

By Raam

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updated over 17 years ago by Raam

2 replies • 14509 views
Discussion

Place Fiducials

Category: Logic Design

By gonuclear

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updated over 17 years ago by gonuclear

1 replies • 14253 views
Discussion

How to count number of paths in RTL-compiler group?

Category: Logic Design

By dkos

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updated over 17 years ago by grasshopper

5 replies • 8557 views
Discussion

How to view the property of Mosfet in my CSM018 technology?

Category: Logic Design

By Henry Hwa

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updated over 17 years ago by grasshopper

1 replies • 13873 views
Discussion

setenv command in RTL Compiler

Category: Logic Design

By dkos

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updated over 17 years ago by dkos

4 replies • 7931 views
Discussion

Problem with ORCAD Capture Simulation

Category: Logic Design

By scdr

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updated over 17 years ago by Amritapuri

3 replies • 6356 views

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