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Logic Design

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  • Discussion

    Hspice Monte Carlo .measure statement use.

    Category: Logic Design

    By pjparekh pjparekh

    •

    started over 16 years ago

    0 replies • 15842 views
  • Discussion

    SOC Encounter

    Category: Logic Design

    By Oysters Oysters

    •

    updated over 16 years ago by gops

    3 replies • 14448 views
  • Discussion

    annotating switching activity

    Category: Logic Design

    By alexsieh alexsieh

    •

    updated over 16 years ago by alexsieh

    7 replies • 17099 views
  • Discussion

    synopsys designware can not be compiled in the conformal Equivalence

    Category: Logic Design

    By misspark misspark

    •

    updated over 16 years ago by tstark

    1 replies • 15353 views
  • Discussion

    can LEC provide cdc check?

    Category: Logic Design

    By zhiweiwu0318 zhiweiwu0318

    •

    updated over 16 years ago by timmynolan

    9 replies • 17744 views
  • Discussion

    Op- Amp loop gain measurement

    Category: Logic Design

    By Saran84 Saran84

    •

    updated over 16 years ago by johannes

    1 replies • 1332 views
  • Discussion

    Wish you Happy New Year.

    Category: Logic Design

    By Raam Raam

    •

    started over 16 years ago

    0 replies • 12727 views
  • Discussion

    RTL Compiler: is there a timing path between 2 FF?

    Category: Logic Design

    By magic magic

    •

    updated over 16 years ago by magic

    3 replies • 13479 views
  • Discussion

    How to save global constrain settings In Allegro?

    Category: Logic Design

    By Raam Raam

    •

    updated over 16 years ago by Raam

    2 replies • 13278 views
  • Discussion

    Place Fiducials

    Category: Logic Design

    By gonuclear gonuclear

    •

    updated over 16 years ago by gonuclear

    1 replies • 13083 views
  • Discussion

    How to count number of paths in RTL-compiler group?

    Category: Logic Design

    By dkos dkos

    •

    updated over 16 years ago by grasshopper

    5 replies • 7824 views
  • Discussion

    How to view the property of Mosfet in my CSM018 technology?

    Category: Logic Design

    By Henry Hwa Henry Hwa

    •

    updated over 16 years ago by grasshopper

    1 replies • 12817 views
  • Discussion

    setenv command in RTL Compiler

    Category: Logic Design

    By dkos dkos

    •

    updated over 16 years ago by dkos

    4 replies • 7436 views
  • Discussion

    Problem with ORCAD Capture Simulation

    Category: Logic Design

    By scdr scdr

    •

    updated over 16 years ago by Amritapuri

    3 replies • 6045 views
  • Discussion

    OrCAD INI File Administrator

    Category: Logic Design

    By pcplod pcplod

    •

    updated over 16 years ago by grasshopper

    1 replies • 13056 views
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