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Logic Design

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  • Discussion

    RC gated clock - automatic insertion

    Category: Logic Design

    By guyra

    •

    updated over 18 years ago by grasshopper

    1 replies • 2851 views
  • Discussion

    Footprints

    Category: Logic Design

    By mohsen

    •

    updated over 18 years ago by tpylant

    1 replies • 14657 views
  • Discussion

    Can't edit.

    Category: Logic Design

    By NeSaM

    •

    updated over 18 years ago by tpylant

    1 replies • 1143 views
  • Discussion

    on Encounter RTL compiler

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by ScreenName

    3 replies • 17061 views
  • Discussion

    Clock tree specification in RtlCompiler

    Category: Logic Design

    By ScreenName

    •

    started over 18 years ago

    0 replies • 14223 views
  • Discussion

    timing_type : non_seq_hold_falling;

    Category: Logic Design

    By guyra

    •

    started over 18 years ago

    0 replies • 14772 views
  • Discussion

    How to convert netlist 2 lib file

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    10 replies • 19847 views
  • Discussion

    Simulating Systemc: ncelab *F,SCILDD error

    Category: Logic Design

    By archive

    •

    started over 18 years ago

    0 replies • 838 views
  • Discussion

    on Nclaunch

    Category: Logic Design

    By archive

    •

    started over 18 years ago

    0 replies • 15136 views
  • Discussion

    Potential multiply driven nets

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    2 replies • 15360 views
  • Discussion

    Potential multiply-driven net (corrected typesetting)

    Category: Logic Design

    By archive

    •

    started over 18 years ago

    0 replies • 14496 views
  • Discussion

    Black Box Mismatches

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    1 replies • 19028 views
  • Discussion

    Bottom_up optimization in BuildGates

    Category: Logic Design

    By archive

    •

    started over 18 years ago

    0 replies • 14260 views
  • Discussion

    LEC Hier-compare when sub modules have extra port in Revised Design!!

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    1 replies • 15690 views
  • Discussion

    Posting Code to the Forum

    Category: Logic Design

    By archive

    •

    updated over 18 years ago by archive

    3 replies • 15608 views
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