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Mixed-Signal Design

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  • Discussion

    How to define a current measurement in ADEXL + Montecarlo using AMS Designer

    Category: Mixed-Signal Design

    By markris markris

    •

    updated over 3 years ago by markris

    13 replies • 13523 views
  • Discussion

    Allowed amount of input wreal data type

    Category: Mixed-Signal Design

    By marzi marzi

    •

    updated over 3 years ago by marzi

    6 replies • 10760 views
  • Discussion

    Apply Input to array in Cadence virtuoso

    Category: Mixed-Signal Design

    By AnubhaSehgal AnubhaSehgal

    •

    updated over 3 years ago by AnubhaSehgal

    2 replies • 9451 views
  • Discussion

    VerilogA: analysis function will not take a string variable

    Category: Mixed-Signal Design

    By NewScreenName NewScreenName

    •

    updated over 3 years ago by NewScreenName

    4 replies • 9813 views
  • Discussion

    corner column not appearing in ViVa

    Category: Mixed-Signal Design

    By bnevins bnevins

    •

    updated over 3 years ago by bnevins

    7 replies • 10786 views
  • Discussion

    How to work with two different GLS netlist which contain same name sub cells in a chiptop AMS simulation?

    Category: Mixed-Signal Design

    By bikram1994 bikram1994

    •

    started over 3 years ago

    0 replies • 7866 views
  • Discussion

    For ADE Assembler, is there an option to "Save simulation data" on specific nets for transient simulation?

    Category: Mixed-Signal Design

    By UniFleSou UniFleSou

    •

    updated over 3 years ago by UniFleSou

    2 replies • 4104 views
  • Discussion

    Priority of netlister when a verilog file is included by AMS Netlister options vs. config view

    Category: Mixed-Signal Design

    By Johanny Saenz Johanny Saenz

    •

    updated over 3 years ago by allenmessina

    2 replies • 9289 views
  • Discussion

    Where is the location of ams simulator which to be put in its path?

    Category: Mixed-Signal Design

    By delgsy delgsy

    •

    updated over 3 years ago by delgsy

    4 replies • 9681 views
  • Discussion

    ERROR (HED-1073) and ERROR (OSSHNL-911) when simulating vhdl + analog blocks

    Category: Mixed-Signal Design

    By delgsy delgsy

    •

    started over 3 years ago

    0 replies • 8798 views
  • Discussion

    What is the right format of "Subcircuit file" for defining "scasubckt" cell in "analogLib" library?

    Category: Mixed-Signal Design

    By fireonthesee88 fireonthesee88

    •

    updated over 3 years ago by FormerMember

    6 replies • 4654 views
  • Discussion

    Xcelium version for cosim

    Category: Mixed-Signal Design

    By paulinho paulinho

    •

    updated over 3 years ago by Andrew Beckett

    1 replies • 9010 views
  • Discussion

    How to add ELDO simulator in cadence virtuoso?

    Category: Mixed-Signal Design

    By sateesh20 sateesh20

    •

    updated over 3 years ago by Andrew Beckett

    1 replies • 9241 views
  • Discussion

    Processing ADC digital output

    Category: Mixed-Signal Design

    By threenca threenca

    •

    updated over 3 years ago by FormerMember

    3 replies • 13069 views
  • Discussion

    How to see all the running simulation?

    Category: Mixed-Signal Design

    By bikram1994 bikram1994

    •

    updated over 3 years ago by Andrew Beckett

    3 replies • 9534 views
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