Mixed-Signal Design

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Discussion

Where to find frac-N pll workshop pll_zambezi45 and saradc

Category: Mixed-Signal Design

By debaabed
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updated over 8 years ago by debaabed

4 replies • 15464 views
Discussion

Connecting SPICE ports inside a SystemVerilog-only testbench

Category: Mixed-Signal Design

By Pacher Luca
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started over 8 years ago

0 replies • 13327 views
Discussion

where does a layout view get verilog module name from?

Category: Mixed-Signal Design

By drdanmc
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started over 8 years ago

0 replies • 13100 views
Discussion

Assura metal Dummy Fill error with NORMAL Target Hierarchy mode

Category: Mixed-Signal Design

By ManuelSuarez
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started over 8 years ago

0 replies • 13065 views
Discussion

Need to plot the delay of ring oscillator versus input voltage of each stage

Category: Mixed-Signal Design

By Abdhkamal
•
updated over 8 years ago by Andrew Beckett

3 replies • 15223 views
Discussion

Current starved delay element

Category: Mixed-Signal Design

By Abdhkamal
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updated over 8 years ago by Andrew Beckett

1 replies • 14118 views
Discussion

Ignoring or avoiding "x" propagtaion for ams simulation for certain signals and/or instances due to connect module definitions

Category: Mixed-Signal Design

By MDiaz
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updated over 8 years ago by Andrew Beckett

3 replies • 4274 views
Discussion

noise analysis- regarding

Category: Mixed-Signal Design

By Charanraj Mohan
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updated over 8 years ago by Andrew Beckett

1 replies • 1762 views
Discussion

VCO based ADC signal transfer function

Category: Mixed-Signal Design

By mohamin
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updated over 8 years ago by mohamin

2 replies • 16353 views
Discussion

WARNING (ADEXL-2410): Multiple entities....

Category: Mixed-Signal Design

By syafiq
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updated over 8 years ago by syafiq

2 replies • 13255 views
Discussion

unable to plot dB20

Category: Mixed-Signal Design

By Charanraj Mohan
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updated over 8 years ago by Andrew Beckett

1 replies • 16406 views
Discussion

No connection module found:Need an input port of continuous discipline electrical, and an output port of discrete discipline logic

Category: Mixed-Signal Design

By PuneethL
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updated over 8 years ago by Andrew Beckett

1 replies • 5333 views
Discussion

how to add lvsIgnore in CDF of a cell made by myself.

Category: Mixed-Signal Design

By chqian
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updated over 8 years ago by Andrew Beckett

1 replies • 13465 views
Discussion

a doubt about global flag in model file of a KIT-in generic

Category: Mixed-Signal Design

By Charanraj Mohan
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updated over 8 years ago by Andrew Beckett

3 replies • 13485 views
Discussion

How to add -spectre_args +mts in AMS UNL

Category: Mixed-Signal Design

By nthoangga
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updated over 8 years ago by Andrew Beckett

1 replies • 2747 views

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