Mixed-Signal Design

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Discussion

requesting to help adding model library in spice netlist

Category: Mixed-Signal Design

By sateesh20

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updated over 3 years ago by sateesh20

2 replies • 10831 views
Discussion

vsource will not accept expressions in its parameters

Category: Mixed-Signal Design

By NewScreenName

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updated over 3 years ago by NewScreenName

2 replies • 9007 views
Discussion

How to define current in verilogams-wreal model ?

Category: Mixed-Signal Design

By bikram1994

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updated over 3 years ago by Andrew Beckett

3 replies • 11525 views
Discussion

CDF callback discrepancies between design variables and hard-coded parameter values

Category: Mixed-Signal Design

By VincentCheung

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updated over 3 years ago by VincentCheung

2 replies • 9398 views
Discussion

Array of design variables for an array of Instances

Category: Mixed-Signal Design

By VincentCheung

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updated over 3 years ago by VincentCheung

2 replies • 10153 views
Discussion

ams simulation does not work with large number of design points

Category: Mixed-Signal Design

By delgsy

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updated over 3 years ago by lornagandy

2 replies • 9796 views
Discussion

Issue with simulating Verilog Functional view

Category: Mixed-Signal Design

By AmarDas

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updated over 3 years ago by AmarDas

2 replies • 10107 views
Discussion

Simulating the instance 50 times

Category: Mixed-Signal Design

By AnubhaSehgal

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updated over 3 years ago by Andrew Beckett

3 replies • 9423 views
Discussion

Verilog A: analog event needed to create a decimal to binary block

Category: Mixed-Signal Design

By NewScreenName

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updated over 3 years ago by FormerMember

3 replies • 17979 views
Discussion

How to define a current measurement in ADEXL + Montecarlo using AMS Designer

Category: Mixed-Signal Design

By markris

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updated over 3 years ago by markris

13 replies • 15226 views
Discussion

Allowed amount of input wreal data type

Category: Mixed-Signal Design

By marzi

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updated over 3 years ago by marzi

6 replies • 11982 views
Discussion

Apply Input to array in Cadence virtuoso

Category: Mixed-Signal Design

By AnubhaSehgal

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updated over 3 years ago by AnubhaSehgal

2 replies • 10333 views
Discussion

VerilogA: analysis function will not take a string variable

Category: Mixed-Signal Design

By NewScreenName

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updated over 3 years ago by NewScreenName

4 replies • 10789 views
Discussion

corner column not appearing in ViVa

Category: Mixed-Signal Design

By bnevins

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updated over 3 years ago by bnevins

7 replies • 11944 views
Discussion

How to work with two different GLS netlist which contain same name sub cells in a chiptop AMS simulation?

Category: Mixed-Signal Design

By bikram1994

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started over 3 years ago

0 replies • 8644 views

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