Mixed-Signal Design

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Discussion

PLL Phase noise simulation in Cadence Virtuoso

Category: Mixed-Signal Design

By asrf
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updated over 5 years ago by Andrew Beckett

3 replies • 25211 views
Discussion

how to setup customized rules file to simulation a circuit with 2 level of voltage 1.8v and 3.3v ?

Category: Mixed-Signal Design

By Nhumai
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updated over 5 years ago by Andrew Beckett

1 replies • 14228 views
Discussion

VCOs with Arbitrary Phase Noise Profile

Category: Mixed-Signal Design

By growingmind
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updated over 5 years ago by Andrew Beckett

1 replies • 14343 views
Discussion

Dynamic Comparator Performance Parameter

Category: Mixed-Signal Design

By ashish2
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updated over 5 years ago by FormerMember

1 replies • 14392 views
Discussion

comparator delay with calculator

Category: Mixed-Signal Design

By Bob Mounger
•
updated over 5 years ago by ashish2

4 replies • 17133 views
Discussion

schematic that uses spectre M_TWO_PI unhappy in ams

Category: Mixed-Signal Design

By drdanmc
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updated over 5 years ago by Andrew Beckett

2 replies • 14244 views
Discussion

Layout in cadence

Category: Mixed-Signal Design

By Priti gupta
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updated over 5 years ago by Andrew Beckett

1 replies • 13559 views
Discussion

Which errpreset takes precedence, APS accuracy+speed or tran analysis?

Category: Mixed-Signal Design

By FormerMember
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updated over 5 years ago by FormerMember

10 replies • 13176 views
Discussion

control verilog search path in virtuoso "check"

Category: Mixed-Signal Design

By drdanmc
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updated over 5 years ago by drdanmc

2 replies • 2522 views
Discussion

Best practices for Verilog-a modelling time variant resistance

Category: Mixed-Signal Design

By LDIL
•
updated over 5 years ago by Frank Wiedmann

3 replies • 16144 views
Discussion

vector net cannot be connected to a spice/spectre instance by port name

Category: Mixed-Signal Design

By PrasadAMSEng
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updated over 5 years ago by J S Mason

4 replies • 4612 views
Discussion

How to use +sv option in AMS simulation

Category: Mixed-Signal Design

By happyy
•
updated over 5 years ago by happyy

2 replies • 17710 views
Discussion

DNL/INL Using Cadence ahdlLib blocks for ADC

Category: Mixed-Signal Design

By growingmind
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updated over 5 years ago by Chrisss

2 replies • 7808 views
Discussion

Calling one macro within another macro in Verilog-a

Category: Mixed-Signal Design

By LDIL
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updated over 5 years ago by Andrew Beckett

1 replies • 15896 views
Discussion

Is there an eval command in Verilog-a?

Category: Mixed-Signal Design

By LDIL
•
updated over 5 years ago by Andrew Beckett

3 replies • 14559 views

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