• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      HASAN2024
      HASAN2024 55 Points
    • 2
      SD20251126912
      SD20251126912 50 Points
    • 2
      SM202511279440
      SM202511279440 50 Points
    • 4
      Aurel B
      Aurel B 42 Points
    • 5
      Don2009
      Don2009 40 Points
  • Leaderboard

    • 1
      steve
      steve 17,724 Points
    • 2
      oldmouldy
      oldmouldy 13,640 Points
    • 3
      eDave
      eDave 10,261 Points
    • 4
      ShawnLogan
      ShawnLogan 9,660 Points
    • 5
      skillUser
      skillUser 7,477 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    Adding text blocks

    Category: Allegro X PCB Editor

    By archive

    •

    updated over 17 years ago by admin

    8 replies • 18405 views
  • Discussion

    SpecctraQuest Hspice DML

    Category: PCB Design

    By wadevb

    •

    updated over 17 years ago by wadevb

    4 replies • 13774 views
  • Discussion

    How effectively HDI (using Blind/Burried Via's) design can be done in Allegro PCB design L ?

    Category: PCB Design

    By girish

    •

    started over 17 years ago

    0 replies • 282 views
  • Discussion

    Assign a net to a mechanical pin

    Category: PCB Design

    By ahmetozsoy

    •

    updated over 17 years ago by ahmetozsoy

    3 replies • 17715 views
  • Discussion

    when and how to use set_clock_latency in RC

    Category: Logic Design

    By BACKMAN

    •

    started over 17 years ago

    0 replies • 13850 views
  • Discussion

    Problems with synthesis using RTL compiler and PKS

    Category: Digital Implementation

    By Renee

    •

    updated over 17 years ago by grasshopper

    2 replies • 14813 views
  • Discussion

    Can SRoute route to the line shape pin of Vdd and GND?

    Category: Digital Implementation

    By Renee

    •

    updated over 17 years ago by Kari

    3 replies • 14329 views
  • Discussion

    Change property name globally

    Category: PCB Design

    By yogeshyogesh

    •

    updated over 17 years ago by steve

    5 replies • 17204 views
  • Discussion

    pls help me,about skill

    Category: Allegro X PCB Editor

    By steven_deng

    •

    updated over 17 years ago by steven_deng

    4 replies • 1647 views
  • Discussion

    how to compile OVM with ncvlog

    Category: Functional Verification

    By codefire

    •

    updated over 17 years ago by codefire

    3 replies • 14997 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information