• Discussion

  OrCAD or Allegro PCB 17.2 version Assign Color, Deassign Color bug Locked

  13816 views
  1 reply
  Latest over 5 years ago
  by steve
• Discussion

  How to add pin to end of a wire Locked

  18784 views
  6 replies
  Latest over 5 years ago
  by Martinsh
• Discussion

  Routing into Multiple Layers

  13549 views
  3 replies
  Latest over 5 years ago
  by masamasa
• Discussion

  vManager vAPI authentication Locked

  15899 views
  4 replies
  Latest over 5 years ago
  by BGarcia
• Not Answered

  CIS - Multiple symbols per library or single symbol per library 0

  9104 views
  13 replies
  Latest over 5 years ago
  by thomasli
• Discussion

  Does OrCAD 17.4 Still Support Back Annotate from PADS Layout?

  20567 views
  11 replies
  Latest over 5 years ago
  by DavidH172
• Discussion

  finding grey colored(uncolred) metals/vias in layout Locked

  1924 views
  1 reply
  Latest over 5 years ago
  by malcolm70
• Discussion

  DRC error when through holes or vias are at the edge Dynamic shape

  12792 views
  2 replies
  Latest over 5 years ago
  by Santosh Vema
• Discussion

  TrueDFM constraint modes

  12689 views
  3 replies
  Latest over 5 years ago
  by Ejlersen
• Discussion

  ERROR EMX in virtuoso Locked

  16855 views
  6 replies
  Latest over 5 years ago
  by Andrew Beckett
• Discussion

  [AWR Microwave Office] Issue related to plot of contours Locked

  12713 views
  0 replies
  Started over 5 years ago
  by Eres
• Discussion

  hiCreateDisclosureTriangle bold fonts Locked

  12868 views
  2 replies
  Latest over 5 years ago
  by Aldo2
• Discussion

  *ERROR* (AMS-1245): AMS UNL netlisting" in AMS simulation Locked

  4822 views
  3 replies
  Latest over 5 years ago
  by Andrew Beckett
• Discussion

  Plotting a Graph in cadence with different axis variables DC-Analysis Design variable Locked

  20001 views
  1 reply
  Latest over 5 years ago
  by Andrew Beckett
• Discussion

  Simulating a DAC in Cadence Locked

  16242 views
  2 replies
  Latest over 5 years ago
  by mirtaji65