Community

DVCon Europe in Munich is coming up on 19 and 20 October. For any Americans reading this and thinking October in Munich means Oktoberfest and beer, I hate to disappoint you. Despite the name, Oktoberfest is largely in September (it ends on the first Sunday...

Increasingly, taking an appropriate ARM^® processor has become the standard way to pipe-clean a digital flow in a new process. ARM processors are widely used and are available at various levels of complexity. For 10nm (what TSMC calls N10), Cadence...

https://youtu.be/Ej7aa83-OFM

Monday: A preview of DVCon Europe on 19th/20th October, where Cadence is presenting 3 tutorials and several papers.

Tuesday: At the Linley Processor Conference, Krste Asanović presnted the RISC-V ISA and then Markus Levy...

I had an interesting conversation with Michiel Ligthart and Rick Carlson of Verific. They have a unique niche in the EDA ecosystem. They provide parsers for SystemVerilog, VHDL, and IEEE 1801 (fka UPF). They really have no competition other than companies...

“Finland is not Scandinavia” was one of the first statements I heard, when I landed in Norway.

“OK, let's consider it as a Nordic country”, I said, trying to resolve the situation.

“Nordic is fine”.

So Denmark...

When I first started programming, the first programming language I learned was Fortran IV. In that era, learning to program at that age was rare, since the only computers that existed were mainframes. This was before the minicomputer, let alone the various...

To address the growing needs for floating-point arithmetic in DSP algorithms, all Tensilica DSP families support floating point. In this second part of a two-part Whiteboard Wednesdays video series, we discuss the scalable floating-point capabilities across Tensilica DSP families that provide developers with the most choice for their application.

https://youtu.be/oTdzedEkVg0

The best way to complete a complex task is to break it into smaller, simpler tasks.

This is exactly what Symbolic Placement of Devices, popularly known as SPD, does for layout engineers. SPD is a symbolic row-based placer. Designed primarily for small to medium-sized designs, SPD displays only the relevant information needed to perform device placement. Using SPD layout, engineers can easily edit device placement…

Well, they told me that starting blog titles with a number is good clickbait. The bigger the number, the better, right? It turns out that there are more Bytes in town than Breakfast Bytes. Cadence has a collection of videos that go under the name Training...

Ethernet was developed in the 1970s and has been a viable communications protocol for over 40 years. Ethernet was initially used to connect computer systems and peripherals in a local area network (LAN) but quickly evolved to be the protocol of choice for wide area networks (WANs) and of course, the internet. It’s been constantly reinvented, with new capabilities, more security, and faster speeds over the years to keep…

I wrote recently about the TSMC OIP Symposium where they talked about future devices: Ge FinFET, III-V FinFet, III-V GAA FET, stacked GAA nanowire FET, tunnel FET, graphene nano ribbon, and carbon nanotube. Why all these weird materials?

If you go to...

Go to any venture capitalist's website and they will have a bragging page with their portfolio. Usually not just their current investments but also (especially) major exits. Bessemer Venture Partners is no different. Here is their top exits page.

ISO 26262 is a functional safety standard applied to the development of electrical and/or electronic (E/E) systems in automobiles. It is aimed at reducing risks of physical injury or of damage to the health of people in the event of an unplanned or unexpected hazard. The standard requires that every tool used within the design and verification flow, that can either insert errors into the final product or prevent errors…

Every year in the fall, the Linley Group runs their processor conference. There are other conferences earlier in the year that are more specialized, addressing servers, mobile, and IoT. The conference, originally called the Microprocessor Forum, has been...

https://youtu.be/dv54rKmMLRo

Monday: Options for 5nm. Silicon can only cut off sub-threshold at 60mV/decade. There are two ways to get more, the blue pill and the red pill.

Tuesday: Training bytes, 1200 videos to allow self-instruction on many aspects...

This year's MemCon is on October 11, at the Santa Clara Convention Center. Last year I wrote about how MemCon got started. But since it was just my fourth blog for Breakfast Bytes, and hardly anyone knew it existed, it wasn't widely read. So I will repeat...

Memcon is an event like few others, where SoC architects congregate to learn and debate the strategies of system design to keep up with the insatiable data/throughput demands of today’s electronics. The topics range from memory technology to system architectures, as captured in the MemCon 2015 Proceedings. While this year’s agenda will provide similar, updated information, there are 3 things you probably don’t know…

Twice a year TSMC has a big meeting in San Jose. These are the times that there is a public update on their process roadmap, how process ramps are going, the OIP ecosystem, and so on. But they make it hard for people like me since their rules are that...

Adventures in Backdrilling

For the past 15 years or so, routing high-speed interfaces handling 5Gbps or higher have become more common in many electrical designs.   Transitioning high-frequency signals between layers can greatly affect signal integrity when a portion of plated through-hole (PTH) is left unused, forming an electrical stub.  In general, these stubs are a source of impedance discontinuities and signal reflections…

System-on-chip (SoC) designers are always optimizing what has become known as PPA, which stands for power, performance, and area. Almost always, the most severe constraint is on power. We can put a lot of functionality on a chip and we can clock it very...

At CDNLive Israel, Yaron Netanel of Mellanox talked about his experience with Palladium ICA mode. ICA stands for in-circuit acceleration.

One basic way of using Palladium is in-circuit emulation or ICE. In this method, the DUT is modeled on the Palladium...

https://youtu.be/1le_bd4o01Q

Monday: System Design Enablement with Cadence and TSMC. Archtiectural power analysis

Tuesday: The keynotes from TSMC OIP Symposium last week

Wednesday: A preview of next month's MemCon

Thursday: The keynotes from...