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CDNLive Silicon Valley 2015 will be held Tuesday and Wednesday, March 10-11, at the Santa Clara Convention Center. For the first time, we’ll have a very interesting 2-day IP track at the conference. Sign up now!

Check out our exciting agenda in Track 7. Some of the highlights include:

• External Memory Architectural Choices for Terabit-Class Devices by Broadcom
• Applying Maslow’s Hierarchy of Needs to IP Reuse…

Cache coherency is not unique to the new ARM® AMBA® 5 CHI (Coherent Hub Interface) specification that enables processors to work together in high-performance, coherent processing “hubs”, and to deliver the high data rates that are common in enterprise markets, such as servers and networking. Coherent architectures have existed for many generations of CPU designs, but verifying adherence to coherency rules has always been…

In this week's Whiteboard Wednesdays video, the last in a three-part series, Kevin Yee explains how MIPI UniPro is becoming a popular standard for chip-to-chip communications.

http://youtu.be/maQXxumlKys

The sparkle seems to have gone out of the Internet of Things (IoT) market for the moment, and this is a problem because it means my Star Trek lifestyle is now on hold.

The ambitious Google Glass project was shelved recently amid tepid market response and cultural backlash. The smart watch market has yet to ramp to early expectations; people seem to be waiting for Apple’s version.

Wearables and other IoT devices…

Functional Verification Debug Blog - SimVision Gems

 Most engineers are familiar with the “Butterfly effect” – the notion that a small change can result in enormous repercussions in the future. A similar notion applies in verification. We might expect waveform traces to match between, say, an RTL simulation and post-synthesis gate-level design for a certain signal, but we want to be sure. We want to ensure no small…

This week, you can view a couple of videos where customers describe how they used Cadence's Allegro TimingVision technology to achieve 4X faster timing closure on DDR3 and DDR4 memory subsystems of their designs and the IPC-2581 design data format and Allegro PCB Editor tools to eliminate surprises at the final stages of PCB design.

Routing boards with high-speed interfaces had been a time-consuming, manual…

Happy New Year to all from the award-winning Virtuosity blog team (Alice, Praveena, Rajesh and myself)!  Okay, so it was an internal Cadence Standing Ovation Team Award, but it works for me.

There are few things I love more than learning and every month (or two) when I look through the new content, I am delighted to see how much high-quality material is available to highlight new features and help you use our software more…

This week, you can view a video where a customer describes how they used the Cadence® Sigrity™ PowerSI® tool to enable their team to run what-if cases to gain insights that lead to useful changes in trace widths, impedance, and more.

Nexus Technology
At Nexus Technology, Joe Socha, signal integrity engineer, is responsible for analyzing tiny PCBs that are used as interposers between memory devices and their…

In this week's Whiteboard Wednesdays video, the first of a two-part series, Avi Behar explains the ARM® AMBA® (Advanced Microcontroller Bus Architecture) protocol family. Many of the protocols, from Advanced System Bus (ASB) and Advanced Peripheral Bus (APB), to Advanced Traced Bus (ATB) and Coherent Hub Interface (CHI), are discussed.

http://youtu.be/fkumTBDElsU

The following enhancements have been made to the 16.6 Allegro PCB Editor Thieving application.

Thieving outline: New ‘Rectangle’ option added to the list. If selected, the user is required to make only two digitizations of a rubber-banded rectangle.

Thieving style: A new ‘Line’ setting has been added to the existing ones of ‘Circle’ and ‘Rectangle’. The fill elements will be created as actual cline/line segment…

High-performance and high-speed memory design characterized by low-power operation are requirements for today’s leading edge electronics. Cadence is a leader in providing advanced process node, low-power memory IP. Recent news with Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and HiSilicon Technologies Co. Ltd highlights our collaboration to meet the needs of industry leaders in this area. This is the first customer…

LAS VEGAS—In the cacophony of CES, it’s refreshing to find an escape. I found mine in a set of headphones slipped over my ears.

Standing in the Cadence booth chatting with Yipeng Liu, with Cadence audio product marketing,  I’m listening to audio using DTS  Headphone:X technology.

As Liu said, “hearing is believing.” If you close your eyes, you find yourself in a room with the audio. It’s a strange experience…

In this week's Whiteboard Wednesdays, Bob Salem discusses voltage and monitoring intellectual property (IP).  Using voltage and monitoring IP to accurately track temperature and turn off hot points can dramatically affect performance, reliability, and battery life, as well as impact applications on the chip. View the video to learn more.

http://youtu.be/5M8WN71Xpi8

Building a system on chip (SoC) from IP blocks requires system-level integration and bring-up, and that requires firmware working on the target. In a fast-paced development cycle, it is crucial to provide customers with IP blocks and tested firmware. In particular, at the bring-up stage, there may be very few debug capabilities at hand and, therefore, a firmware package that is pre-tested on multiple platforms and systems…

I attended the IEEE 802.3 meeting in Atlanta last week. I have blogged about Ethernet standards-making meetings before and I thought I should post an update on how things have progressed. Cadence has a comprehensive design and verification IP portfolio for Ethernet, and we strive to keep it aligned to the current standards.

Before I dive in, I'd like to share some pictures from Atlanta; the third picture shows the vault…

"Throw it over the wall" is business slang for completing your part of a project and then passing it off to the next group. This phrase is usually said when there is little communication between two groups.—answers.com

I have noticed that a common scenario is for the engineers who developed the Universal Power Format (UPF) files for a device to throw it over the wall to the verification engineers assigned…

Recently, while at a customer site, I was faced with the huge task of looking for all instances of a specific module to find a particular signal assignment. My first thought was to do a grep search, and then go through each file to see where that particular assignment occurred. This seemed easy enough in theory, so I set out to do it. What I was not prepared for was:

1. Not knowing where the source files were actually…

In this week's Whiteboard Wednesdays video, the second of a two-part series, Jeffrey Chung discusses 32-bit applications and how LPDDR4 can be used most effectively.http://youtu.be/6XvqFAu0z7A

Learn more about Cadence IP.

LAS VEGAS—As the mobile world matures, opportunities abound for optimizing the user experience. For instance, voice commands now trigger a variety of functions and applications (think Siri and "Ok Google"), but they not only require the system to be on, they chew up battery life.

This challenge is about to fade. Realtek Semiconductor came here to CES 2015 to demonstrate at the Cadence meeting suite one…

It seems to be a fact of life that software has bugs and, unfortunately, our software is no exception. In most cases, however, it is not the bug itself that causes you grief. Rather, it is the fact that analysis, workaround, and shipping the fix to you sometimes takes a long time, and requires a lot of deep interaction between the user and Cadence R&D developers. Although in an ideal world, the process…

LAS VEGAS—A key function of automotive, IoT, security, and similar applications is the ability to detect faces and take action. But it's got to be done in an efficient, power-sensitive manner. 

Here at CES 2015, Gary Dick, Cadence engineering product manager, and Pulin Desai, Cadence product marketing director, showcased face detection using an Xtensa processor with an IVP image/video DSP and a MIPI PHY and controller…

In this week's Whiteboard Wednesdays video, the first of a two-part series, Jeffrey Chung discusses new LPDDR4 standard features that reduce power consumption and increase performance.  Low-voltage interface standard logic (LVSTL) and data byte inversion (DBI) are discussed in detail.

www.youtube.com/watch

LAS VEGAS—The annual International Consumer Electronics Show (CES) here is not just about amazing new technologies, although that's what captures the public's attention. It's about the electronics design ecosystem that enables those products.

The Cadence meeting suite may traditionally be tucked away from the crowds near the back of South Hall 2, but it's no less a hive of activity involving members…

After nearly a week at CES, almost everyone is asking me – what was the big thing? I’m excited to say that there was no one big thing. The show is so huge that there were many big things!

If anything, the show itself was the big thing. It was so huge and had something for everyone! There was absolutely no way to see it all.  Spread among 2.2 million square feet of exhibit space with more than 3600 exhibitors…

A voltage-controlled oscillator (VCO) is an electronic oscillator whose oscillation frequency is controlled by a voltage input. The applied input voltage determines the instantaneous oscillation frequency. Consequently, modulating signals applied to control input may cause frequency modulation (FM) or phase modulation (PM).

The Rapid Adoption Kit (RAK) referenced in this blog explains modeling VCOs in AMS Simulator (PSpice…