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In this week's Whiteboard Wednesdays, Lou Ternullo explains NAND Flash and the need for advanced error correction. Lou also details the Berlekamp Chaudhuri Hocquenghem (BCH) algorithm. Learn how this algorithm is implemented and how engineers are using it in their designs today.

Using proven Cadence Verification IP (VIP), you can verify SoC designs faster, more thoroughly, and with less effort. While innovating and providing great products and technologies, the VIP team at Cadence also believes that it is important to keep creating self-help knowledge resources. These resources provide an easy way for you to learn about and stay productive with these products, technologies, and methodologies…

There is always a demand for learning something simply and quickly on your own in some corner of the world. The big challenge that I have faced with learning is how to find the right learning vehicle that helps me discover what I didn't already know in a short period of time. If you also struggle with this aspect, you should surely look at Cadence's Rapid Adoption Kits (or RAKs), available at https://support…

Cadence was the first IP provider to bring PCIe Gen3 Controllers to the market. Since then, our PCIe offerings have evolved to include the lowest power PHY solutions available, FPGA platforms for prototyping, software drivers, and the industry’s leading verification IP.

Compliance: Last year, the PCI-SIG began official Gen3 compliance testing. The Cadence PCIe controller achieved Gen3 compliance in 2013.…

Cadence Online Support, https://support.cadence.com/, provides access to support resources including an extensive knowledge base, access to software updates for Cadence products, and the ability to interact with Cadence Customer Support.

In the June release of Cadence Online Support, many new features and functionalities were added to help users filter and narrow their search results, to provide feedback opportunity…

Just a short post today.

In the 16.6 Allegro PCB Editor release, multiple region shapes can now be assigned to a single region constraint object. Using the General Edit Application mode, pre-select multiple region shapes, then use the context-sensitive RMB menu to access the Assign to Region command.

Ensure you are in General Edit Application mode. Consider an example where we will assign the region shapes associated with…

In this week's Whiteboard Wednesdays, we take a little different approach and show you a fun and fast way to understand how Cadence® Tensilica® Xtensa® processors work, and how you can easily use them to offload your applications processor. After the video, learn more about Xtensa processors here: http://bit.ly/1xZfYdP. 


www.youtube.com/watch

Excuse the tennis analogy, but just coming out of Wimbledon!  However, EDA and academia have had a long-standing tennis match, if you will, in which there is a "give and take"  between the EDA world and the many universities around the world. At Cadence, we have an extensive University Program and, through the years, we have worked closely on everything from developing curriculum (using our software, of course…

Application Notes

1. Setting PVS to QRC av_extracted Flow with tsmc28 (& tsmc40) LVS

Shows you how to put in place the PVS(LVS)-QRC(av_extracted) view using TSMC files.

Videos

2. Mismatch Contribution in Virtuoso Analog Design Environment GXL

Mismatch contribution analysis is a Monte Carlo post-processing feature that helps in identifying the important contributors to mismatch variation. You can then modify…

The register and memory package vr_ad for Specman is used in pretty much every verification environment. In most cases today, the register specification is captured in an IPXACT description and the register e-file can be automatically generated from it.

The vr_ad package comes with a variety of pre-defined register access policies, which cover the typical register usage.

However, many users have the need for special…

The 16.6 release of Allegro PCB Editor has several new enhancements for team design work (design partitioning) that help reduce the number of .DPF (design partition file) import/export iterations the PCB Design team experiences in the physical team design flow.

Flexible Boundaries
Designed to reduce the number of iterations between the master and partition designers, it’s now possible for partition designers to move components…

The 16.6 Allegro PCB Editor now has IPC 2581 data transfer capabilities. Thanks to Ed Hickey – the Allegro Sr. Product Engineering Manager - for preparing this information below.

Read on for more details …

IPC 2581 Overview

PCBs have changed significantly over the past three decades, yet to the surprise of many, we still commonly use 30-year-old ways of communicating design intent to manufacturing. These decades…

Hi Folks,

Check out this great new video on YouTube:

CDNLive SV 2014: PMC Improves Visibility and Performance with Spectre APS

In this video from CDNLive Silicon Valley 2014, Jurgen Hissen, principal engineer, MSCAD, at PMC, discusses an aggressive...

The PCI-SIG has (FINALLY) released the PCIe 4.0 rev 0.3 specification for members' review, just in time for the annual Developer Conference at Santa Clara, CA, next week (June 4-5).

The Gen4 spec was announced 2.5 years ago with the 'usual' objective - doubling the bandwidth while keeping backward compatibility. Sounds easy, doesn't it? Well - the time it took to get to rev 0.3 hints that it's not a trivial…