Community

TUTORIAL: Fast Track Your UVM Debug Productivity with Simulation and Acceleration

Session: 5T on Thursday, Feb. 28^th from 8:30AM - 12:00PM

For more details on the debug tutorial, click here

This debug tutorial will highlight how customers can reduce their debug turnaround time by employing the most efficient debug tools available. Class based software-oriented environments are best debugged using interactive debug techniques…

With the 16.6 release, you now have the capability of utilizing the PCB SI tools (SigXP) to work with topologies and constraints in the OrCAD Capture environment.

Capturing constraints early in design cycle is important for the following reasons:

• Quality challenges as the design cycle for any PCB product is shrinking day by day
• As the edge rates are shrinking, it is necessary to constrain the critical signals up-front to…

This month's highlighted content includes helpful information on wreal modeling, mixed-signal interoperability, verification of digitally-calibrated analog circuits, device and block-level routing and lots more.

Enjoy and don't forget to leave feedback at the top of the individual content pages in COS (Cadence Online Support) to let us know what information you find most useful.

Rapid Adoption Kits

1. Guidelines on…

Technology leaders like IBM continuously seek opportunities to improve productivity because they recognize that verification is a significant part of the overall SoC development cycle. Through collaboration, IBM and Cadence identify, refine, and deploy verification technologies and methodologies to improve the productivity of IBM’s project teams. 

Tom Cole, verification manager for IBM’s Cores group, and I took a few…

I love it when I'm sitting in a meeting with my colleagues or with a group of customers and someone brings up something about our software that they find annoying and another person says "Wait, why are you doing it that way?  Why don't you just...".  Immediately my mind says "blog time!" 

One such sequence of events happened recently around the concept of "drag and drop."  For those of…

The 16.6 Allegro Design Workbench (ADW) Configuration Manager has been enhanced!

There is an enhanced focus on software serviceability and an improved ease of use environment for managing:

• Software updates & version status
• Configuration Files & Database updates
• Single cockpit to monitor global server topology
  • Easy to use dashboard for Server connection status
• Server topology

A new ADW Server Setup Wizard provides the…

After Cadence acquired Sigrity in July 2012, we heard many of the same questions: What is happening with my favorite Sigrity tools? Is Cadence going to change the functions and features I’ve been working with several years? If I’m not a Cadence Allegro user, can I continue using Sigrity tools without purchasing any other tools? If I’m a Cadence Allegro PCB SI user, what changes am I facing now?

Everyone knows that the increasing speed and complexity of today's designs implies a significant increase in power consumption, which demands better optimization of your design for power. I am sure lot of us must be scratching our heads over how to achieve this, knowing that manual power optimization would be hopelessly slow and all too likely to contain errors.

Here are 8 Top Things you need to know to optimize your…

As described in Specman Advanced Option appnote, Specman Elite supports dynamic load and reseeding. This allows the user to run the simulation up to a certain point (often until right after reset) and save the simulation. The user can then restore the simulation and run many different tests either by changing the random seed (reseeding) or by loading additional e files which will change the test, e.g., adding constraints…

At the upcoming DVCon (in San Jose, CA February 25-28), Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here).  However, Team Verify would like to alert users of Cadence Incisive formal and multi-engine tools, apps, and assertion-based verification (ABV) to the following papers and posters focused on this domain.

* Session 2, Tuesday Feb. 26, 9-10…

At the upcoming DVCon (in San Jose, CA February 25-28), Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here).  Of course, Team Specman cannot resist drawing your attention to the many activities that will feature Specman and e language-related content, or be of general relevance to Specmaniacs.  Hence, if you are going to the conference, please consider…

Most verification customers claim that they are spending over 50% of their verification effort in debug. If so, you should check out these latest SimVision debug videos since you will quickly see how SimVision can enable you to be much more productive in less than an hour after viewing the videos.

Take the time to browse through these videos.  Everyone will benefit, even if you are a new user looking for a debug solution…

The Allegro FPGA System Planner (FSP) 16.6 release offers major improvements in Auto-interactive pin swap (“Planning Mode”) with the addition of “Auto pinswap” functionality. Using three different algorithms – Reassign Bundle Pins, Rake Order, and Breakout Order – you can re-optimize entire bundles (the existing 16.5 manual pin swapping functionality has been retained). The communication between …

What can designers do about advanced node technology? This is an introduction to the Cadence Virtuoso Advanced Node design environment, announced Jan. 28, 2013, as a custom/analog design development environment for leading edge-advanced node technology.

Problems of Advanced Node Design

When designing with the most advanced node technologies including 22nm technology and beyond, you will encounter many new problems that no…

Components in a design communicate with each other based on some rules or protocols. These protocols contain a group of signals with some relationships defined between them -- for example byte lanes, clock and strobes. The Allegro Design Entry HDL 16.6 release enables the use of these protocols or signal grouping by introducing support for hierarchical interface definitions.

These definitions can be entered in the design…

Random generation is always a complex task, and differences in results are usually very hard to debug. Besides, generation misbehavior always rings many bells in R&D :-)

A customer reported a random stability issue, explaining that the generator (IntelliGen) generated different values with the same seed. One simulation was started from vManager, the other in a Unix shell, and they ran in different run modes (compiled…