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Japan’s semiconductor industry is undergoing a significant change in recent years. We are seeing a shrinking business in SoC development while design and semiconductor companies are trying to focus more on higher profitable and differentiable products like microcontrollers and power management ICs. Most such designs are mixed-signal designs and hence the demand for technologies and innovations in this area is very…

The Allegro PCB SI Signal Setup and Audit commands were introduced in the 16.5 release. Enhancements have been made to these commands in the 16.6 release.

Read on for more details…


Selection of all Components in Component Class Setup

A new top level has been added to the tree display with a label of All Classes. Selecting the All Classes item will cause all of the visible classes and components to be selected:

More…

Preface: on Tuesday December 11 we are giving a free a webinar on "ACE Assertion-Based Dynamic, Formal, and Metric-Driven Verification Techniques with ABVIP".  Register today: http://goo.gl/rmBhh

As anyone who has worked with ARM's AMBA 4 AXI^TM Coherency Extensions -- a/k/a the "ACE^TM" protocol -- knows, there are a ton of different configuration options and operational scenarios available to the designer…

In this posting of we show yet another implementation of sumlist using an operator which will be new to many readers. While…

Functional verification is the biggest challenge in delivering more complex electronic devices on increasingly aggressive schedules. Every technique for functional verification relies on a fast simulation engine for execution, so performance is of prime importance to all users.

Simulation performance can't be a single number or optimization because each environment is unique in terms of the methodology deployed, the languages…

If you are a Specman vr_ad user, you probably know that register access is implemented  using the read_reg / write_reg. For reading/writing a register, you have to

1. Extend a vr_ad_sequence

2. Add a field of the type of the register you want to access

3. In the body() , call the read/write_reg

For example:

extend MAIN vr_ad_sequence {

    !tx_data_reg : VR_AD_TX_DATA  vr_ad_reg;

    !tx_mode_reg : VR_AD_TX_MODE  vr_ad_reg;

    body() …

Greetings,

I've saved my favorite for last....here's a preview of the changes to the nport component in MMSIM12.1.

1.  The Edit Object...

Recently an EDA industry observer relayed some Specmaniacs' concerns about satisfying the increasing demand for e/Specman trained verification engineers in Europe and other geographies.   Team Specman is seeing this growth too, and here is what we [Cadence] are doing to help:

* First, we have a network of expert e/Specman service providers located around the world (many of which who can support projects in geographies…

Are you working in the area of mixed signal?

Then you may want to exchange information and experiences with other engineers.

At the Cadence Community, a new Mixed-Signal Design Forum has been launched, providing a place to discuss topics that cross between analog and digital domains.

It doesn't matter if you're just starting with mixed-signal design, or you have a lot of experience. This is a customer-driven forum that…

The recently concluded ARM TechCon 2012, the annual event for ARM users (including hardware and software engineers) along with ARM ecosystem partners, was a huge success. Once again, this event showcased the excellent Cadence-ARM partnership that's helping to bring next generation electronic designs to fruition for our customers.

Cadence had a huge presence at ARM TechCon. On the first day (Chip Design Day) Cadence h…

In some designsflows, you need to connect two plane shapes on the same net, but on different layers, together with vias in order to improve connectivity. These “shorting” vias are placed in a regular pattern across the overlapping areas of the shape, in such a way as not to interfere with any routing on layers between the two shapes.

The 16.6 Allegro Package Designer (APD) product now provides a mechanism…

The trend of combining analog and digital circuits on a single chip has been growing for several years. More recently I'm seeing more and more designers improve their productivity by transitioning their designs to Open Access (OA) and taking advantage of the interoperability between Virtuoso and the Encounter Digital Implementation (EDI) System.  Whether you're performing floorplanning in Virtuoso (schematic-driven…

MMSIM 12.1 contains many new features to aid RF designers. Here's a preview of the changes...

Documentation Improvements

The SpectreRF User Guide is being completely rewritten and updated for MMSIM12.1.  Check it out - I'm sure you'll really...

Working with the conventional Specman C language interface has two major disadvantages:

1.       There is a tight dependency between the e code and the C code. The user must include the Specman header file which was generated based on the e code. Every minor change in the e code requires regeneration of the header file.

2.       The C interface doesn't support calling e TCMs (Time Consuming Methods) from C code.

Let's take a look…

The Component Alignment feature is available in Placement Edit Application mode. It was introduced in the Allegro PCB Editor 16.3 release and now enhanced in 16.6 to support the following new options:

• Alignment Edge
  • When aligning vertically, select ‘left’ or ‘right’ as the edge to base the alignment on
  • When aligning horizontally, select ‘top’ or ‘bottom’ as the edge to base alignment on…

The SPB 16.6 Release is available! You can download it from the Cadence Software downloads site.

Here are just a few press announcements on the 16.6 release –

New Allegro 16.6 Release Accelerates Timing Closure on High-Speed PCB Interfaces by 30 to 50 Percent

Announcing OrCAD 16.6—A One-Two Punch for Mainstream PCB Engineers

Cadence Allegro Accelerates Product Creation Through Efficient Collaborative ECAD Environment…

The well attended Mixed-Signal Technology Summit last month really demonstrated the tremendous interest our customers have in learning new methodologies and techniques for mixed-signal designs. I would like to share some interesting data points based on a survey from the attendees of the event. Among the close to 200 attendees, 73% were designers with analog centric design experiences. However, about 24% of them declared…

Last week over 35 power users from over a dozen companies came together for the latest installment of "Club Formal" -- a user group meeting exclusively focused on topics in formal analysis and Assertion-Based Verification (ABV).  This instance of Club Formal featured several papers from Silicon Valley power users on expert-level techniques, as well as highlights of new "verification apps" that are highly automated…