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The current Allegro PCB Power Integrity (PI) tool is fast, but not accurate enough in the high frequency band due to the effect of discontinuities. This feature uses a discontinuity model in the PI analysis. With discontinuity model integration, PI analysis is more accurate and allows you to control the target impedance more efficiently.

A plane pair can be simulated by an equivalent circuit of a grid of transmission…

The nport component located in analogLib can be used in circuits for Spectre and SpectreRF simulations. It is a scattering parameter (S-parameter) based distributed multi-port element. The nport truly is a "black box"… It can be used to model dramatically...

The SPB16.3 Allegro PCB Editor has a new 3D Viewer!

Viewing a 3D rendering of the Allegro design is now available with the 3d_viewer (View — 3D View) command. The 3D Viewer is invoked in a separate window which includes viewing filters; choice of solid, wire frame or transparent graphics; and controls to pan, zoom, and spin the display.

 

The 3D viewer also operates in pre-selection mode. This mode makes it possible…

At DVCon 2011 I had the opportunity to catch-up with NextOp's CEO Yunshan Zhu, where in this video he shares some anecdotes about the BugScope's performance in real world customer environments (including accelerating assertions in Palladium with -0- (zero, zip, zilch, nada) hardware overhead!), and how their technical success is to translating to the bottom-line.

If the video fails to play, click here.

Note: we…

We interrupt our technically oriented blogging to shamelessly promote a free webinar we are giving on SoC Connectivity checking this Thursday March 24 at 10am-11am Pacific time.  At first glance, this topic doesn't seem like such a big deal - after all, checking IP-to-IP and point-to-multi-point connections is usually done by a well-organized Co-Op student, or obviated by using some sort of "correct by construction" methodology…

A Chinese design engineer told me that his manager once told him:  "You do not have to have creativity but you must know how to imitate!" This is kind of a reflection of the rapid technology growth in China for the past decade, where many of the technology advancements came from learning the latest and best technologies from the West.

When we planned for the worldwide Cadence EDA360 Tech-On-Tour mixed-signal…

As more and more custom/analog designs migrate to advanced process nodes (<65nm), design teams are being confronted with an ever-increasing need to better manage the impact of parasitics throughout the entire custom/analog design flow. In addition, more and more layout design teams are finding themselves drawn into the front-end design team's simulation flow and their path to parasitic closure.

But why is a new…

Object Linking and Embedding (OLE) support in SPB16.3 Allegro Design Entry CIS (or Capture) allows you to embed or link an object on your schematic page. The object types that you are allowed to embed or link are defined by the applications and files available on your computer. This feature allows you to annotate your schematic pages with any external data (information) that you need to enhance the usability and readability…

Smaller process technologies are enticing chip makers with bigger rewards from their end products. The shorter gate lengths at 28nm promise faster transistor speeds and less leakage power, and can double the amount of the logic that can be put into the same die area. Most importantly, however, more die on a wafer means lower per unit cost. 

Meanwhile, design complexity is compounded as chip content grows significantly…

Software, like fine red wine, can get better with age as well -- but it requires constant advancements to remain a vibrant contributor.  Such is the case with the Virtuoso IC6.1.5 custom/analog technology release, which delivers on the promise of Silicon Realization with capabilities that maintain design intent throughout the custom/analog flow, simplify the abstraction of analog information to provide high-performance verification…

• How do I simulate a transmit mixer?

• How do I look at both upper and lower sidebands?  

• How do I set up my simulation for PAC and Pnoise?

• When I plot my data, how do the indexes correspond...

The ADW16.3 Allegro Design Workbench has a desktop cockpit that allows engineers to view their internal design processes and the applications applicable to each of the steps in their flow. The Workbench guides the engineer through the flow and provides a consistent approach to otherwise disparate processes across the entire design team. The Allegro Design Workbench (ADW) is fully configurable so that it can be modified…

At DVCon 2011, a paper presented by Freescale and Cadence described a truly novel application of formal technology for something completely different than assertion-based verification (ABV).  Specifically, the authors used formal engines to optimize the selection of complex (read, "higher in area and power consumption") vs. simple (read, "lower power, lower area") power control flip-flops. In this short video, one of the…

Clearly UVM 1.0 was the main story at DVCon last week, but there was other big news in verification IP that bears repeating.  Specifically, last week Cadence announced a new Verification IP ("VIP") Catalog -- a complete combination of standards-based Cadence and ex-Denali verification IP, supporting 3rd party simulators and hardware-assisted verification.  In this video taken on the DVCon 2011 expo floor, my colleague…

The DVCon 2011 conference was held this week and the Accellera Universal Verification Methodology (UVM) 1.0 release is breaking records in term of interest and attendance.  UVM 1.0 is a big deal(!) The core functionality is solid and ready for deployment.  Accellera held a full day tutorial on UVM 1.0 on Monday.  And during a panel discussion on Tuesday afternoon, AMD and Intel announced that they are in the process…

As I write this, I've just returned from the most important conference and tradeshow of the year for functional verification: DVCon in San Jose. The "DV" officially stands for "Design and Verification" but most people think that it means "Design Verification" since the focus has been almost entirely on functional verification in recent years. This week's conference was dominated by two big themes…

I wrote about the new Cadence Online Support features in one of my blog posts last year.

One of our Silicon Package Board (SPB) Customer Support AEs suggested that I include the Cadence Online Support Product Page URL whenever I write about a specific product’s feature. I will be doing that -- a great idea! While my first post talked about some highlights of the product pages, I thought I’d take this week to review the…

Are you looking for new approaches to improve your verification productivity by 40 - 60%? Look no further... read the technical application note by Corey Goss on how to Improve Verification Productivity through Adopting Dynamic Load and Reseed Methodology. Attached is a link to the application note that provides the technical details and the benefits of using this new advanced functionality. 

Specman Advanced Option Appnote…

The other day a designer E-mailed me: How can we rename a net in Encounter?

I followed up to clarify whether the designer wanted to change the net associated with routed wire segments, or wanted to rename a signal net. He clarified that he wanted to change a logical signal net's name.

Changing the net name associated with a routed wire segments is described in this solution:

editSelect -nets VDD1
editSelectVia -nets…

Next week my colleagues and I will be at DVCon 2011 in force, ready to regale you with technical papers, panels, and techtorials covering the full range of functional, assertion-based, mixed-signal, and transaction-level verification topics.  If you are within a tank of gas or a Southwest flight of San Jose, going to DVCon is a no brainer.  I guarantee that you WILL learn something -- whether it's from the aforementioned…