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Verification: Cadence Investment in SystemC Continues -- NASCUG SystemC Day at DVCon

Steve Brown

Don't lose touch with what's new in the world of SystemC! Cadence is a long time contributor and sponsor of SystemC initiatives, and that commitment continues to show during next week's SystemC Day and North American SystemC User Group (N...
- 24 Feb 2011
Digital Design: Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Signoff

PeteMc

Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a chip that is so compelling …” in his previous blog, I would like to help you understand how Cadence is using our signoff qualified engines during the design implementation flow to reduce your time to tapeout.

Anyone remember the story of the tortoise and the hare from your childhood? The moral of the story…
- 23 Feb 2011
Analog/Custom Design: Q&A: IBM Modeling Team Describes Advanced SOI Qualification Flow In Cadence MMSIM Platform

archive

Circuits implemented using sub-micron technologies require designers to meet tighter and tighter specifications despite increasing statistical variation and complexity. High correlations between actual silicon and circuit verification using advanced SPICE models are therefore a must to ensure first pass design success. This characterization requires a high degree of cooperation and integration between modeling engineers…
- 23 Feb 2011
System, PCB, & Package Design : What's Good About PCB SI Signal Quality Screening? SPB16.3 has a Few New Enhancements!

Jerry GenPart

Signals are subject to degradation when they are transmitted through a channel. High speed signals are especially susceptible to degradation as loss and distortions tend to be frequency dependent. Channel characterization and multi-million bit simulations can be used to investigate these issues in greater detail. However, such investigations are time consuming for PCBs with several high speed nets.
Signal Quality Screening…
- 23 Feb 2011
Verification: Celebrating the UVM 1.0 Release, or the Gadfly Eats a Little Crow

tomacadence

As I hope you have all seen by now, Accellera has announced the official production release of the Universal Verification Methodology (UVM) 1.0 standard. My colleagues Richard Goering, Stan Krolikoski and Adam Sherer have already blogged about the release and its contents so I'll refer you to their posts rather than cover the same ground here. What I really want to do is to congratulate the Accellera VIP Technical…
- 22 Feb 2011
Verification: The Increasing Role of SystemC in System Design

jasona

Today's post is less technical and a bit more theoretical, but I promise that my next post will be more hands-on.As somebody working on virtual platforms in an EDA company, I regularly spend time talking to firmware and embedded software engineer...
- 22 Feb 2011
Verification: Formal Driven MDV – A New Tool for your Toolbox

Team MDV

Have you considered adding formal to your metric driven verification flow? Maybe now is the time, as it has never been easier within Incisive Enterprise Manager to combine results coming from formal assertions with results coming from simulation, and visualize both at the same time. You see the results of simulation, the results of formal, side by side, truly enabling you to utilize the right tools for the job.

More importantly…
- 21 Feb 2011
Verification: Being a Part of Something Truly Remarkable - UVM

Adam Sherer

For just over two years I have had the honor of playing a role in a dramatic example of EDA360 in action -- the creation of the Accellera UVM standard 1.0. I could not be more proud!
Many will measure UVM 1.0 in terms of features, but it is much more than that. It represents a different way of conducting the business of verification in today's electronics industry. Our business is changing -- the cost of finer process…
- 18 Feb 2011
Verification: The Tale of the Silicon Re-Spin and the Bug That Got Away

tomacadence

I'd like to continue my blog series discussing corner-case conditions of various kinds that I have encountered in my engineering career. So far they've all had happy endings. I discussed a software bug that was only in a prototype, not an actual product, so no real damage was done. I described a subtractor bug and a class of interface bugs in hardware, all of which were caught in verification prior to chip fabrication…
- 17 Feb 2011
Digital Design: Evolution of Design Exploration and Planning

archive

The great architect Frank Lloyd Wright once said "you can fix it on the drafting board with an eraser, or on the construction site with a sledge hammer." The semiconductor design industry is a perfect example where finding issues later in the flow can be extremely expensive. Chips that fail in high-volume consumer products can cost companies hundreds of millions or even a billion dollars, and there is huge benefit…
- 17 Feb 2011
Digital Design: Guest User Blog: dbShape For All Your Logical Operation Needs

BobD

This is a guest post from Jason Gentry at Avago. I hope you enjoy this useful piece he's contributed on using the Encounter Digital Implementation System's dbShape command that debuted in 10.1.
I figured it was time for another guest blog, especially since I've been able to play with one of the new-to-EDI10.1 commands called "dbShape." During CDNLive! 2008, one of the topics I talked about was…
- 16 Feb 2011
System, PCB, & Package Design : What's Good About Allegro Router and Highlighting? You’ll need the SPB16.3 Release to See!

Jerry GenPart

Just a quick post this week on a new Allegro PCB Router feature in the SPB16.3 release. A small feature, but very useful!
Highlight/Unhighlight bbvias

The following command is accessible in SPB16.3 SPECCTRA to highlight/unhighlight selected kinds of blind and buried vias (bbvias):

highlight <object_type> [<start_layer> [<finish_layer>]] on|off

object_type::= bbvias | blind_vias | buried_vias

start_layer…
- 16 Feb 2011
Verification: The Role of Coverage in Formal Verification, Part 3

TeamVerify
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In the last post of this series, we will address the last but not least of three key questions to be answered with coverage in formal verification:
How good are my formal constraints? (Addressed in Part 1)
How good is my verification proof? (Addressed in Part 2 and "2A")
And today's question, "How can I feel confident my verification is complete…
- 14 Feb 2011
Verification: Why the Demand for Acceleration and Emulation is Growing

Ran Avinun

The dream of any marketer is a growing demand for its product line. Let me start this blog by quoting the System Realization (part of the Cadence EDA360 strategy) section from the transcript of the recent (Q4) Cadence earnings call. "In A...
- 14 Feb 2011
System, PCB, & Package Design : Shorter, Predictable Design Cycles (SPDC) – Ensuring Critical Signals Have a Return Path

hemant

This is third in the series of blog posts about making your design cycles predictable and shorter for dense PCBs that have highly constrained high-speed interfaces such as DDR2, DDR3, SATA II/III, and USB 3.0. The first post talked about using ECSets to ensure that the interfaces are designed correctly, and that the system provides feedback with all the changes that come along the way. Changes can come from, but…
- 14 Feb 2011
Analog/Custom Design: Analog Assertion Based Verification Methodology – Reality or a Dream? (Part 2)

archive

The design and verification methodology for analog circuits has not changed much over the past decade. But the complexity of analog designs has grown exponentially. Analog parts are not just on the peripherals of SoCs any more. It is very common to have complex analog IP in applications such as communications, transportation and bio-medical devices. So it is not enough to just verify analog designs in isolation.
There…
- 9 Feb 2011
System, PCB, & Package Design : What's Good About Allegro Measure, Grids and Formulas? See For Yourself in SPB16.3!

Jerry GenPart

This week, I’m tossing together a mix of a few new SPB16.3 Allegro PCB Editor features.

Show Measure any Layer

In the SPB16.3 release, the show measure (Display — Measure) command now measures the separation between any two objects regardless of the layer. For padstacks, the active layer as shown in the Options panel is used to determine the layer of interest. If the padstack doesn't exist on that layer then…
- 9 Feb 2011
Analog/Custom Design: Advanced Mixed-Signal Designs Demand a Unified Methodology

nizic

Mobile, automotive, consumer and medical applications require the productive realization of large and complex mixed-signal systems in silicon, and they must be on time and within budget constraints. Process capabilities make it possible to implement analog and RF circuits in CMOS technology at advanced nodes, and to integrate analog and digital functionality at the system-on-chip (SoC) level. However, mixed-signal SoC…
- 6 Feb 2011
Verification: De-Mystifying SystemC: What is TLM?

Jack Erickson

In my last post I briefly mentioned that when designing hardware with SystemC, you do not need to allocate logic to register boundaries. And I said that was a blog post for another day. The first step is to separate the core functionality of th...
- 3 Feb 2011
System, PCB, & Package Design : Team Allegro Continues Demonstration of New PDN Analysis Technology at DesignCon 2011

TeamAllegro

Today at DesignCon, drop by the Cadence booth to see TeamAllegro continue the demonstration of our new power delivery network (PDN) analysis technology for PCB design and analysis. See how during the pre-route phase of PCB design, plane shapes can be planned and optimized along with the PCB stackup. Analysis will show where resonant frequencies are likely to exist and adjustments can be made to planes, the stackup, and…
- 2 Feb 2011
System, PCB, & Package Design : What's Good About Capture Locking Objects? The Secret's in the SPB16.3 Release!

Jerry GenPart

The Allegro Design Entry CIS (Capture - Allegro flow) now includes an object locking feature. This feature allows you to temporarily lock and object on your schematic or board while you are cross-probing. This will help to avoid shifting (with the potential of breaking connectivity) a component on the schematic or board during the cross-probe operation.

When you cross probe between Capture and Allegro PCB Editor, you…
- 2 Feb 2011
System, PCB, & Package Design : Cisco and Cadence Present Co-design Paper at DesignCon

TeamAllegro

Today at DesignCon, be sure to drop by Room 203 at 11:05 and see Cisco and Cadence present a paper that embedded.com told their newsletter subscribers will “capture the essence of the presentations at the conference and the quality of the techn...
- 1 Feb 2011
System, PCB, & Package Design : Team Allegro Showing New PCB PDN Analysis Technology at DesignCon 2011

TeamAllegro

Today at DesignCon, drop by the Cadence booth to see TeamAllegro demonstrate the new power delivery network (PDN) analysis technology for PCB design and analysis. This is important because higher speed technologies such as DDR3 require lower voltages. Lower voltages provide less margin for IR drop caused by power and ground planes that are carved up to meet design miniaturization requirements.
However, locating an IR…
- 1 Feb 2011
System, PCB, & Package Design : Team Allegro to Boost Power of PCB PDN Solution – Sneak Peek at DesignCon 2011

TeamAllegro

The Cadence booth at DesignCon 2011 will provide visitors with a demonstration of new technology that has been developed for analysis of the power delivery network (PDN) of a printed circuit board (PCB). This new technology features enhanced static IR drop analysis, and is the foundation of a complete re-design of the power integrity tool that Allegro PCB users have worked with for over ten years.

The new PDN analysis…
- 31 Jan 2011
Verification: What Could Be Simpler than a Request-Acknowledge Handshake?

tomacadence

My last few blog posts have included three corner-case conditions that led to bugs, one in software, one in hardware, and one in real life. One of the reasons that corner-case conditions are missed is that some engineers don't spend enough time really thinking about their design and documenting its intended functionality. Writing specifications that are orthogonal to the specific hardware or software implementation…
- 31 Jan 2011

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