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Recall that three main questions need to be answered to attain coverage in formal verification:

• Part 1 of this series addressed, "How good are my formal constraints?"
• In Part 2 we showed debugging of over-constraining with help of examples, addressing the question, "How good is my verification proof?"
• In a subsequent post we will address the third key question "How can I feel confident my verification…

Here are just some of the new capabilities available in the ADW16.3 Allegro Design Workbench (ADW) Library Revision Manager (LRM) and Component Browser (CB)

• LRM:
  • Detects deleted parts and models
• Component Browser:
  • Identifies parts removed
  • Identifies pre-released parts
  • Identifies parts with lifecycle  warnings
• Design_reports
  • Pre-release models and parts
  • Deleted models and parts

Some features of fixing deleted parts / models:

• Navigate…

1.1: (defun walkCvHier (cv consume)
1.2:   (foreach inst cv~>instances
1.3:     (walkCvHier inst~>master consume))
1.4:   (consume cv))

Just to reiterate: this…

There is no doubt in my mind that assertions will play a significant role in analog verification, be it verifying individual analog blocks or a complete mixed-signal SoC in the near future. So yes, it is for real and it is here to stay. I hope to convince you in this blog that you should take a closer look at adopting assertion based verification (ABV) for your next mixed-signal design. I have worked on assertions extensively…

Kicking off 2011, my colleague Alok Jain -- a Distinguished Engineer at Cadence who directs the company's R&D efforts in formal verification -- spoke with Industry Insights columnist Richard Goering.  In a wide ranging interview they discussed formal verification usage trends, benefits, roadblocks, appropriate coverage metrics, and the growing alignment of simulation and formal to speed Silicon Realization.

In this…

As noted in the prior installment of this series, there are three main questions to be answered with coverage in formal verification:

• How good are my formal constraints?
• How good is my verification proof?
• How can I feel confident my verification is complete?

In Part 1 we began to address the first question, and in this post we will continue to discuss it in the context of debugging over-constrained verification environments…

The SPB16.3 release of Design Entry HDL (DEHDL) provides an easier method for setting up the PCB SI model library path, and brings more consistency to the Front-to-Back (F2B) and Back-to-Front (B2F) flows.

Signal Integrity (SI) models are essential for running an SI simulation. PCB SI is an integrated solution with DEHDL and Allegro PCB Editor. When a design is moved from one engineer’s system to another engineer’s system…

A recent customer blog interview with Geoffrey Faurie from ST Microelectronics and Richard Goering from Cadence was posted on Cadence.com with the title: "Is e or SystemVerilog Best for Constrained-Random Verification?" This blog post has received much positive feedback from other Specman/e and SystemVerilog users. Whether you are a Specman/e and/or SystemVerilog user, this blog provides a good balance of the…

Advanced verification customers are seeing their verification environments getting more and more complex requiring millions of lines of code spread across hundreds, even thousands of files that are re-used from Block --> SoC --> System level. Today's design under test (DUT) can be extremely complex and, as a result, verifying every feature, in every mode of operation, under all conditions is extremely difficult to achieve…

So I know you tell your kids this, you tell your spouse this, you heard it from your parents and they from theirs, yet somehow when it comes down to it -- it always seems easier to "do" than to "plan."  Even redo seems easier than to actually spend the time to write out a meaningful plan and then execute to it.  So why does the recent Cadence verification news revolve around the verification plan…

As with every new release, a primary focus for the Allegro Package Designer (APD) PCB IC Packaging tools is the wire bonding capabilities. These are some of the most frequently used, complex, and crucial commands in the tool. As the majority of packages today are still based on wire bond technology, and this is getting only more important with new technologies like stacked dies and silicon interposers, an intense focus…

Simulation failures are seen quite often in design verification.   Fortunately, with the new Cadence Silicon Realization approach, you'll have the tools necessary to quickly get back to simulating.  The complete solution for determining what is causing your simulation to fail is SimVision, part of the Cadence Incisive Enterprise Simulator. 

You probably saw the recent press announcement, "Cadence Boosts Verification…

We interrupt R&D's Vinaya Singh's excellent series on "The Role of Coverage in Formal Verification" to reference a related post from Richard Goering on "Extending Metric-Driven Verification (MDV) to Formal Analysis - What, Why, and How".  Specifically, Richard's article shows how coverage from formal analysis (described by Vinaya) is tied into what has been a traditionally dynamic simulation…

Last May, I posed a question about what EDA360 means for verification engineers. Yesterday we made an announcement about verification for Silicon Realization that is a big deal. We are delivering a lot of new technology with immediate and high value to verification engineers everywhere. My colleagues will be blogging on many of the details, so let me focus on what I think are the three biggest announced verification…

Facing a verification overrun, you poached resources, clocked overtime, and kept the slip to a few weeks.  Momentarily proud of your diving catch, your GM just told you to get out on the road to sell an additional 400,000 units or your program will be canceled. As you examine every customer looking for the elasticity that will keep you profitable, you plan to find a new approach to Silicon Realization.

This is the reality…

Even before the snap you need to check the environment statically to eliminate bugs. The 700+ rules in…

Previously I wrote about the basics of feedthrough insertion in Encounter.  Today I'd like to push into a tiny but powerful example of how Encounter's feedthrough insertion solution can derive solutions that enable rapid top-level design closure.

Feedthrough insertion in Encounter has two modes of operation: Placement-based -or- route-based.  The advantage of route-based is its awareness of congested vs. sparse areas…

Happy New Year!

Electromagnetic Solution 2D (EMS2D) is designed for accurate transmission line parameter extraction over a full frequency range from DC up to the frequency of interest. However, this accuracy depends on an accurate and complete physical model provided to the solver by users. For example, the parameter for conductor surface roughness is missing from the input parameter list to the solver.

In multiple GB…

The way SKILL++ deals with functions is a bit different than the way traditional SKILL deals with them. In this posting I'd like to show how to implement a design hierarchy traversal engine in SKILL++ and use it as an introduction to SKILL++.

What is SKILL++?

SKILL++ is a subset of the SKILL language, not a separate language as one might suppose. The term SKILL++ refers to a small but powerful set of extensions…

In a recent blog post, I talked about learning a public lesson on the importance of software verification while an intern at Digital Equipment Corporation (DEC). Since I spent most of my early career as a logic designer, not a programmer, I figure that an example of a corner-case condition from that part of my life would also be nice to share. This story will doubtless remind you of a well-known "divide …