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SoC and IP: PCM (now with carbon nanotubes!) programming current drops two orders of magnitude

archive

A fascinating Masters thesis written by Feng Xiong details the fabrication and testing of a phase-change memory (PCM) element using carbon nanotube FETs and “microbubbles” of GST to create extremely small, non-volatile memory elements. (GST is the chalcogenide glass material usually employed as the phase-change media in PCM and widely used as the active material in recordable CDs and DVDs.) Fusing a GST microbubble with…
- 26 Aug 2010
SoC and IP: Seagate and Samsung to jointly develop enterprise-class SSD controller -- a little more info

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A bit more than a week ago, HDD leader Seagate and NAND Flash leader Samsung jointly announced that they would cooperate on the development of an SSD controller. The announcement mentions “Seagate's leadership in enterprise storage technology” and “Samsung's flash memory technology specific to 30 nanometer-class MLC NAND.” There’s a little more information in a blog posted the same day by David Szabados, who manages the…
- 26 Aug 2010
Verification: All I Really Need to Know About MDV I Learned From Hollywood - Part 1

tomacadence

True story: this series of blog posts is inspired by a dream. I recently gave a presentation on the Cadence verification business to our CEO and several members of the Executive Management Team. Naturally, I took this presentation seriously and spent a lot of time preparing the material and thinking through the key points to cover in the limited time I would have with this high-powered audience. The prep work must have…
- 25 Aug 2010
SoC and IP: 8 key takeaways for system design teams from the Flash Memory Summit

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Cadence’s Senior Manager of Technical Communications and a longtime EDA observer Richard Goering attended the recent Flash Memory Summit held last week in Santa Clara, California and came away with eight key ideas that closely tie memory to system design. The first four are:

Memory may be the most important part of your system.

You have to understand the end-user applications to choose a memory subsystem.
…
- 25 Aug 2010
Analog/Custom Design: Things You Didn't Know About Virtuoso: Outputs Setup in ADE XL

stacyw

Continuing on our exploration of ADE XL (see here and here for previous articles), today let's take a look at the Outputs area in the center of the screen.

Any output signals or expressions which appear in the ADE XL Test Editor (or the ADE L window if you created the setup in there) will show up automatically in the Outputs Setup tab. You can still work with them the same way you always have by bringing up the Test…
- 25 Aug 2010
System, PCB, & Package Design : What's Good About Capture Objects Look and Feel? You Can Change Them in SPB16.3!

Jerry GenPart

The SPB16.3 release of Allegro Design Entry CIS (known as Capture) has some cool new features! You can now change the look and feel of a wire or a net on a schematic page by changing the color, line style or line width. Also, Capture now allows you to alter the look and feel of the hierarchal block to change the color of a specific block in your design.
Read on for examples and details....

Changing the wire or bus look…
- 25 Aug 2010
SoC and IP: Kingston DDR3 RAM cracks 3Gtransfers/sec barrier, achieves 3.068 Gtransfers/sec amid clouds of supercooled nitrogen

archive

Mix liquid nitrogen and Kingston’s HyperX DDR3-2333 SDRAM modules and you get 3068 Mtransfers per second (DDR3-3068). That’s what Benjamin “Benji Tshi” Bioux and Jean-Baptiste “marmot” Gerard demonstrated to a packed room full of gamers on August 21 at the recent Gamescon event held in Cologne, Germany (as reported by Softpedia). Boosting SDRAM transfer rates using liquid nitrogen to cool semiconductors below 77K (− …
- 25 Aug 2010
Digital Design: CDNLive! Silicon Valley Abstract Deadline Extended 1 Week

BobD

The deadline for submitting abstracts to CDNLive! Silicion Valley 2010 has been extended 1 week to Sunday August 29th. The conference begins October 26th at the Fairmont Hotel in San Jose, California.
If you've already submitted an abstract: Thank you!
If you haven't yet, I'd highly recommend you take a moment to consider taking part in this year's conference. I think the most common reason people don…
- 25 Aug 2010
Verification: System Realization Webinars Start Sept 8th

Steve Brown

Starting September 8th Cadence will be hosting a series of webinars about various topics in the area of System Realization. Several of these webinars will be led by members of the System Realization Alliance, sharing their particular views and contri...
- 24 Aug 2010
SoC and IP: OCZ accentuates the positive (SSDs) and eliminates the negative (low-margin DRAM modules)

archive

PC add-on vendor OCZ has announced today that its future is in SSDs and high-speed DRAM. The company plans to discontinue low-margin, commodity level DRAM module products in favor of add-ons with higher margins. OCZ's commodity DRAM module products currently represent roughly 70% of the Company's overall DRAM module revenue but over the past six quarters, said the company, the commodity DRAM module product line has operated…
- 24 Aug 2010
Verification: Performance Tips and Tricks: Another Specman Performance Series

teamspecman

Building on the great success of Efrat Shneydor's previous blog series, Performance-Aware e Coding Guidelines, a new "Specman Performance Handbook" was added to the 9.2 release of Specman Elite that included, on top of the previous blog items, a slew of other important tips and techniques on how to create more performance friendly code. Below is the first in a 5 part series of blogs based on excerpts from…
- 23 Aug 2010
Verification: Report On Chelsio’s DAC Case Study In Formal Verification

TeamVerify

As the leader of the Formal Verification R&D team, I'm always fascinated by the many ways our customers apply the tools we build. This year's Design Automatic Conference (DAC 2010) in Anaheim, CA, provided a wealth of examples thanks to a whole user track dedicated to "Case Studies in Formal Verification". The first paper in this series was titled "Leveraging Formal Techniques for Packed Based Designs…
- 23 Aug 2010
SoC and IP: Embedded SSDs: SanDisk’s iSSD puts 64Gbyte SATA SSD on a BGA device measuring only 16x20mm, 1.85mm high

archive

The convenience of SSDs that look like HDDs is that they can seamlessly plug and bolt into the same mechanical and interface infrastructure as their mechanical brethren. Many, many embedded designs would happily forego the mechanical compatibility in exchange for a smaller volumetric requirement because many embedded systems, like nearly all mobile devices, are quite short on extra volume. That’s precisely the market…
- 23 Aug 2010
SoC and IP: Steve Wozniak talks about the importance of memory in system design

archive

Last week at the Flash Memory Summit, Steve Wozniak gave a keynote presentation where he strolled down memory lane, so to speak, and discussed how important memory decisions were to the development of the many systems he’s created. Memory capacity and cost strongly influence every project’s system-level design decisions and Woz’s projects are no exception. Cadence’s senior manager of technical communications Richard Goering…
- 23 Aug 2010
SoC and IP: SSDs versus HDDs: Comments on that giant, yellow, flashing, caution light

archive

A couple of weeks ago, I noted the continued disparity between SSD and HDD pricing in a local advertiser’s newspaper ad and got several interesting responses on LinkedIn. (See The differential cost between SSDs and HDDs continue in today’s Fry’s ad. Giant flashing yellow caution light for SSDs.) Here’s a particularly thought-provoking response from Dave Byrne in Swindon, UK:

"On Steve's original question with regards…
- 23 Aug 2010
Digital Design: Webinar: SOI Gives More Performance Per Watt, And There's An Easy Path

archive

If you've seen any of the recent buzz lately around Silicon-On-Insulator (SOI), you'd know that it's an excellent option that can enable you to meet lower power consumption and die area targets without sacrificing performance or functionality. This is why Cadence, ARM and IBM have partnered to provide you an easy path to silicon with the SOI process for your digital design, including production proven software, design…
- 20 Aug 2010
SoC and IP: NAND Flash in Space: JPL’s Strauss reports advanced Flash devices with finer geometries better for space-borne applications

archive

Yesterday, I blogged about a presentation on embedded SSDs given at the Flash Memory Summit by Viking Modular Solutions during a panel on embedded Flash. Today, I want to discuss the subsequent talk on the same panel, a presentation by Karl F Strauss of NASA’s Jet Propulsion Lab (JPL). Strauss discussed the use of Flash memory for data storage in spacecraft. You might think that shrinking device geometries make newer…
- 20 Aug 2010
Verification: Inside The Virtual File System

jasona

As part of my ongoing effort to report and explain interesting topics related to Virtual Platforms, I have published a new article on the ARM DS-5 Virtual File System over at blogs.arm.com.Please head over and take a look to find out more a...
- 19 Aug 2010
SoC and IP: SSD Form Factors: Viking Modular Solutions talk at Flash Memory Summit explodes the possibilities

archive

Everyone “knows” what an SSD looks like. It looks just like an HDD, usually in a 2.5-inch form factor with a SATA connector. However, that’s not the only possible form factor, not by a long shot. Yesterday, at the Flash Memory Summit, Viking Modular Solution’s Flash Product Marketing Manager Steve Garceau stepped through a series of alternate form factors in a session on NAND Flash SSDs for embedded applications. I found…
- 19 Aug 2010
System, PCB, & Package Design : What's Good About Deleting Parts in ADW? You Can Easily Do This In ADW16.3!

Jerry GenPart

Part, Schematic, Footprint and Models can all be deleted from the database now with the Allegro Design Workbench ADW16.3 release. Schematic and footprint models may only be deleted if they are not associated with a part. Once a Schematic or Footprint model is deleted from the database, the model is removed from the reference library. The deleted model archive is retained in the vault so the Librarian can check out and…
- 18 Aug 2010
Analog/Custom Design: Analog Design vs. Automation -- Why Are They At Odds?

archive

Back in 2002 and 2003 there was a lot of talk about analog synthesis being the "next new thing" to close the productivity gap between analog and digital designers. Well, I hope you didn't hold your breath for this!

That promise failed mostly because analog design was still a custom design challenge, relying on innovation to provide differentiation in the final application. Standardizing analog design…
- 17 Aug 2010
SoC and IP: Andy Walls of IBM talks about NAND Flash for Enterprise Applications

archive
Just got back from a morning spent at the Flash Memory Summit. The last talk I listened to was the pre-lunch keynote from IBM’s Andy Walls, a Distinguished Engineer who has worked at IBM for 29 years and has lots to say about enterprise storage. Walls started his keynote by discussing the 4-legged stool for a great SSD strategy. The four stool legs are:

Enable Enterprise MLC (multi-level cell) NAND Flash. You do…
- 17 Aug 2010
SoC and IP: Intel’s SSD roadmap starts appearing on the Web

archive

Any company in the SSD business knows it must face Intel, so there’s always wide interest in knowing Intel’s plans in this arena. Over the weekend, notices of a pretty thorough chart showing Intel’s SSD roadmap for the next 18 months started to appear on several Web sites. The latest site to carry the image of Intel’s SSD roadmap slide is the IT industry’s biggest online newstip sheet, The Register.

If you seek the…
- 16 Aug 2010
SoC and IP: AgigA Tech DDR3 memory module combines SDRAM and NAND Flash for data backup on one module

archive

AgigA Tech, a memory-module vendor and a subsidiary of Cypress Semiconductor, has added a DDR3 module to its family of high-speed, battery-free, non-volatile SDRAM systems. These new AGIGARAM modules combine DDR3 SDRAM with NAND Flash devices on one registered DIMM. All members in the AGIGARAM product family merge NAND Flash, DRAM, and ultracapacitor power storage to create highly reliable, non-volatile memory systems…
- 13 Aug 2010
Verification: I Think, Therefore I Blog (Cogito Ergo In Araneam Scribo)

tomacadence

I realized that I have just passed the second anniversary of my first blog post, which caused me to ponder a bit about this relatively new vehicle for communication. This is fair warning: some of you may find this post to be self-indulgent piffle. If so, feel free to ignore it, but you have to swear that you've never followed any of the Twitter twits who engage in self-indulgent piffle all day, every day ("I'm driving…
- 13 Aug 2010

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