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  • RF Engineering: New Time-Saving Feature in IC6.1.4 ISR2: Plot S-Parameter Data Directly From ViVA!

    Tawna
    If you haven't heard about it....there is a new feature in IC6.1.4 ISR2 which makes troubleshooting circuits containing nports (s-parameters ) much easier and faster!
    Starting in IC6.1.4 ISR2,  you can now plot s-parameters directly in ViVA (without having...

  • System, PCB, & Package Design : What's Good About ADW Part Lifecycle? Numerous Improvements in the SPB16.3 Release!

    Jerry GenPart

    The SPB16.3 release of Allegro Design Workbench (ADW) now adds several new key features to the part and model status capabilities.

    As a part moves through its part lifecycle, ADW provides the ability to control how that part behaves.


    These new features include:
    • A “Development” status for library development operations
    • Part lifecycle for business operations
    • Ability to define behavior based on part’s lifecycle…

  • SoC and IP: Party on at DAC, says Denali

    archive
    Denali DAC Party Logo 2010Back by popular demand, the Denali DAC party. The big one. With the bells and whistles. With the idol contest. The one with the outrageous and copious quantities of music and fun. Oh yeah, and copious amounts of alcoholic beverages. That one.

    Want to go? It’s all on you. To get a ticket, you’re gonna’ need to register here: http://a.denali.com/4H. Then you need to get to Denali’s booth first thing Monday morning at…

  • RF Engineering: Using RF Simulation Technology for Analog Applications

    Hany
    The particular nature of analog circuits puts restrictive requirements on circuit simulators. The EDA industry has introduced proven shortcuts to deliver simulation speed and accuracy for specific applications, e.g. Harmonic Balance for RF and partitioning...

  • Verification: UVM World Community Site Now Available!

    tomacadence

    Yesterday morning, the verification world was buzzing with the first release of the Universal Verification Methodology (UVM) standard library and documentation from Accellera. This represents a major milestone for Accellera as well as for the EDA industry, since it is the first time that all the major verification vendors have aligned on a single methodology.

    Yesterday afternoon, Cadence followed up the Accellera release…

  • SoC and IP: 1.8-inch SSD with PATA interface targets mini Notebooks, Netbooks, good for embedded apps too

    archive
    Active Media Products 1.8-inch SSD With all of the recent SSD announcements, you might think that the only form factor and interface for an SSD would be 2.5 inches and SATA. This blog has covered some other SSD advances such as SSDs with PCIe interfaces at the high end, but there’s another end to consider. Many Netbooks and mini Notebooks still have IDE/PATA interfaces and employ 1.8-inch HDDs. Further, many, many embedded systems have the older IDE/PATA…

  • Verification: UVM - 10 Years in the Making ...

    mstellfox

    In case you the missed the news today, the Accellera VIP TSC released the first version of the Universal Verification Methodology (UVM).  This represents a significant achievement on the part of the TSC as it is the first standard SystemVerilog Base-Class Library and Methodology.  While there has been a lot of hard work by many members of the TSC since December of last year when the OVM was chosen to be the basis of the UVM…

  • SoC and IP: Toshiba stands on 2Xnm NAND platform with devices, SSDs, and hybrid storage

    archive
    Last week, Toshiba’s president and CEO Norio Sasaki stood firmly upon a leading-edge NAND Flash technology platform as he discussed his company’s future plans for memory and storage development, as reported by Nikkei Business Publications’ Tech-On!. Sasaki said that Toshiba plans to move forward with 2Xnm Flash processing by this summer, having already achieved volume production of 32nm NAND Flash devices in March. Sasaki…

  • Verification: Initial Release of the UVM Now Available!

    tomacadence

    As Richard Goering just reported, the Accellera VIP Technical Subcommittee (TSC) this morning posted the first release of the Universal Verification Methodology (UVM), tagged "1.0 Early Adopter" since there is a bit of new technology beyond the OVM 2.1.1 baseline. This is great news for the verification community; at last we have a single library and methodology around which we can rally.

    I've been somewhat of…

  • System, PCB, & Package Design : DDR3 Timing issues? Watch the Allegro PCB SI / TimingDesigner Webinar!

    TeamAllegro
    Last year, TimingDesigner improved the interface to PCB SI and many of our joint customers have taken advantage of performing static timing analysis on their fully routed boards using the two tools together. However, DDR3 adds a whole ’nother level of complexity with its faster speeds, lower voltages, programmable ODT, derating tables, write leveling, and on and on.

    Fortunately, the folks working on…

  • SoC and IP: Early Adopter release of UVM now available

    archive
    Accellera has been working on a new industry-standard verification methodology called the UVM (Universal Verification Methodology) and an Early Adopter release is now available here if you wish to start using the UVM today. The UVM distribution kit contains a User Guide, a Reference Manual, and an open-source reference implementation of the work completed to date. Mentor’s Dennis Brophy wrote a blog last month that said…

  • Verification: EDA360: Cool People Creating Cool Stuff

    jasona
    Now that we have had some time to reflect on the meaning of EDA360, it occurred to me that one of the goals of EDA360 is to make EDA cool (or cooler than it already is). One way to do this is to contribute to the cool parts of products people see, li...

  • Digital Design: What you didn’t know about DFM for advanced node designs: “In-route” is insufficient

    Manoj Chacko

    Recently, there has been a lot of buzz about addressing DFM issues during routing. This is not a surprise as the economics of increased development cost of advanced process nodes and manufacturing has influenced dramatic changes to business models of several semiconductor companies. Due to the increasing design cost and time-to-market pressure, a re-design or few weeks delay, because of poor yield for example, may mean…

  • SoC and IP: SSDs in embedded control: cold rolling steel in old European factories

    archive
    By far, most application stories connected with SSDs revolve around servers and PCs. There’s a vast, hidden market in embedded industrial controls, where PC-like process controllers manage large machinery on a daily basis. Decades ago, these process controllers were simple state machines. In fact, they started as relay-based devices. Now, of course, they’re all processor-based. An article that appeared this week on the…

  • SoC and IP: CADENCE TO ACQUIRE DENALI

    archive
    Complementary Transaction Supports Cadence’s EDA360 Vision
    SAN JOSE and SUNNYVALE, Calif. -- May 13, 2010 -- Cadence Design Systems, Inc. (Nasdaq: CDNS), a leader in global electronic design innovation, and Denali Software, Inc., a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that the companies have entered into a definitive merger agreement under which…

  • System, PCB, & Package Design : Economic Recovery on the Way to the Airport

    Team OrCAD
    Last week, one of the members of TEAMOrCAD took a trip to China. The ride to the airport was provided by one of the local airport transportation service companies. In the course of talking with the driver on their way to the airport, Kevin (the driver) mentioned that the company was in the process of re-hiring drivers as business had been picking back up over the last many months; mainly experiencing an increase in business…

  • SoC and IP: Mass marketing methods come to SSDs

    archive
    Newly introduced and available for pre-availability orders, the privately branded 2.5-inch SSDs from established Apple Mac component vendor OWC (Other World Computing) are a sign of the rapidly changing SSD landscape with respect to mass marketing of solid-state drives to end users. The Mercury Extreme Pro series of SSDs range in capacity from 50 to 480 Gbytes and they physically look pretty much like every other SSD…

  • System, PCB, & Package Design : What's Good About SCM and Packageable Schematics? The Secret's in the SPB16.3 Release!

    Jerry GenPart

    Many customers want to use System Connectivity Manager (SCM) known as Allegro System Architect (ASA) for quick prototyping and then start using the traditional schematic based PCB design flow. Now with the Export Schematic feature available in the SPB16.3 release, you can use System Connectivity Manager to quickly capture design logic, especially for high pin-count devices and its associated connectivity, and then generate…

  • SoC and IP: Enterprise-class HDDs due to disappear, soon. All hail the enterprise-class SSD.

    archive
    The great Grand Poobah of SSD research Jim Handy released an industry report on Enterprise SSDs last month. Enterprise applications are currently where SSDs really shine because enterprise users can translate time into money far more easily than can clients running PCs and laptops. Because SSD speed improvements are so easy to justify in terms of total cost of ownership, SSDs are quickly finding welcome spots in all manner…

  • SoC and IP: Last call for free DAC tix

    archive
    The DAC 2010 (DAC47) free exhibit passes program has been a big success with more than 1000 free exhibit passes already claimed. If you’re procrastinating, ask yourself “Why haven’t I signed up for a free exhibit pass yet? Is there really a zero-percent chance that I’m going to DAC?”

    If there is zero chance you’re going to DAC and you’re in the business of designing ICs, then you’d better ask yourself another couple…

  • Verification: Inside Cadence: Training for EDA360

    jvh3

    Over the past few weeks all of Cadence's Verification and Systems Solutions Applications Engineers (AEs), Services Engineers, and many Customer Support staff, have been brought together for detailed methodology and product training.  The objectives of this ambitious undertaking are to bring their skills up to date, brief them on all the roadmaps, and in general prepare them for the challenges expected in the coming…

  • Verification: FMCAD Call for Papers Extended to May 12

    TeamVerify

    Team Verify would like to inform you about the final call for papers for FMCAD 2010 (Formal Methods in Computer-Aided Design), being held 20-23 October 2010 in Lugano, Switzerland. 

    This conference has traditionally focused on research on formal methods in academia and industry.  However, this year the conference is expanding to bridge the gap between research and real world applications, supported by a whole new "industrial…

  • SoC and IP: SSDs don’t need disk interfaces. Case in point: OCZ’s USB 3.0 SuperSpeed Enyo

    archive
    Most SSDs are designed to be interface- and form-factor-compatible with existing rotating mass storage devices (aka: hard drives or HDDs). However, that need not be the case. Many SSD vendors are making significant sales by offering SSDs with alternate interfaces. Fusionio’s SSDs are based on PCIe for example. Perhaps the SSDs with the highest unit volume are lowly USB sticks, although their performance leaves a lot to…

  • SoC and IP: New White Paper discusses the challenges of chip design based on AMBA 4

    archive
    ARM’s series of AMBA specifications have become a de facto standard for SoC (system-on-chip) interconnects. ARM introduced the first version of the specification more than 15 years ago and has now released the latest version of the specification, called AMBA 4. The AMBA 4 specification is actually a collection of specifications (including AXI4, AXI4-Lite, and AXI4-Streaming) that may well revolutionize the future of high…

  • SoC and IP: Memory Market Outlook for 2010: How Bad (or Good) is it?

    archive
    If you’ve been following the roller-coaster ride that constitutes the global semiconductor memory market, then you’re probably looking over the shoulders of as many memory analysts as possible, trying to find one whose crystal ball isn’t cracked, fused, melted, or blackened. Memory analyst Lane Mason recently spent some time at Denali Software and recorded a Webcast with his overview of recent events in the global memory…
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