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In this week's Whiteboard Wednesdays video, Kishore Kasamsetty will help you learn more about how LPDDR4X can cut down a significant amount of DRAM and SoC PHY power with the use of a 0.6V VDDQ signaling level. LPDDR4X is also available in the highest performance timing bins- 4266 Mbps. Silicon proven LPDDR4X IP in many popular nodes is available from cadence making it ideal for applications requiring high bandwidth with…

The JEDEC UFS (Universal Flash Storage) started in 2011 with the v1.0 first specification version, supporting a bandwidth of 300 MB/s per lane. Since then JEDEC has been continuously releasing new UFS specification versions on top of the MIPI UniPro® and MIPI MPHY® evolving specs. UFS is now evolving to a new version of 3.0, reaching a total bandwidth of 2.4 GB/s. It seems that UFS keeps on slowly winning over eMMC in…

In this week's Whiteboard Wednesdays episode, Nick Heaton, Distinguished Engineer, Cadence, describes the verification challenges for SoCs when integrating CCIX (Cache Coherent Chip-to-Chip Protocol) IP.

https://youtu.be/XJo0FieHEYc

When defining coverage bins for coverage items, the number and size of bins depend on the item type. People seek ways to define the MIN and MAX value of the type automatically, rather than typing the numbers.

For example, to ensure edge values are covered, we want to have a bin of the MIN value of the type, a bin of the MAX value of the type, and the rest of the values – to be grouped in 10 bins. If the field is of unsigned…

Thanks to Xcelium, there’s a new feature on the block in SystemVerilog. It pertains to real number modeling (SVRNM), and it both enhances and simplifies the design of mixed-signal circuits.

How? Well, for example, in the process of pixel design for image sensors, a designer may need to have several real nets share a value at the same time. This effectively makes those nets shorted together for the required duration…

Cache coherency is not a new concept. Coherent architectures have existed for many generations of CPU and Interconnect designs. Verifying adherence to coherency rules in SoCs has always been one of the most complex challenges faced by verification engineers. Over the years, it became even more challenging with increasing number of cores in CPU clusters and introduction of the embedded L3 (level 3) cache to the coherent…

Let me tell you a funny story.

We’ve been working with an outside research agency to write an eBook with new insights into ECAD data management. And based on the findings, I wanted to write a blog about how risky it is to just put your ECAD data on a network or shared drive with a file and folder structure. I thought I had a pretty solid first draft of that blog post written before going away for Christmas.

We…