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Latest Blog Posts

  • Breakfast Bytes: Arm Security Manifesto...and Krack

    Paul McLellan
    Paul McLellan

    breakfast bytes logoThe Internet of Things (IoT) could be a big number...20 billion things... 50 billion things... or Arm's favorite number all week at TechCon, a trillion things. Or it could be a lot closer to zero if people don't trust the things in the first place....

    • 10 Nov 2017
  • Digital Design: How to Measure and Improve Design Regularity for Better Yield

    Philippe Hurat
    Philippe Hurat
    The following post is an excerpt of “Methodology for Analyzing and Quantifying Design Style Changes and Complexity using Topological Patterns” that Jason Cain, Principal Member of the Technical Staff with AMD gave earlier at the SPIE...
    • 9 Nov 2017
  • Breakfast Bytes: Social Engineering

    Paul McLellan
    Paul McLellan

    breakfast bytes logo

    The biggest weakness in security are the people. It is almost never the encryption algorithms themselves, or anything technical like that. Last year, Science Daily reported that many people will apparently give out their passwords for chocolate:

    ...
    • 9 Nov 2017
  • System, PCB, & Package Design : How to Be Sure Your PCB Design Is Protected from ESD Events

    Sigrity
    Sigrity
    One way to determine if your design can withstand an electro-static discharge (ESD) event is to test it in the lab with an ESD gun. It might work. But it might not. If it does not, it is going to be a time consuming and expensive process to find a wa...
    • 8 Nov 2017
  • Verification: Adding Annotations in Your e Code

    teamspecman
    teamspecman

    If you have had a chance to work with languages like Java or C#, you might have come across Annotations. Since the Specman 17.10 version, annotations have become part of the e language! (See Java annotation and Basic Introduction to Data Annotation in .Net Framework.)

    What are annotations? Annotations are a form of metadata that provides information about an entity in your code. However, they have no direct effect on…

    • 8 Nov 2017
  • The India Circuit: The Exciting New Product Launched at CDNLive India 2017

    Madhavi Rao
    Madhavi Rao

    One of the highlights at CDNLive India 2017 that was held in September was the launch of the new memory characterization solution from Cadence called the Legato Memory Solution.

    Vinod at CDNLive India

    I had a chance to speak to Dr. Vinod Kariat, Corporate VP of R&D at Cadence...

    • 8 Nov 2017
  • Breakfast Bytes: Simon Segars: It's the Security, Stupid

    Paul McLellan
    Paul McLellan

    breakfast bytes logo

    Simon Segars opened the second day of Arm TechCon (or for exhibitors who didn't notice the first day since they were setting up, the first day). Simon, of course, is the CEO of Arm, although Arm is no longer a public company since Japan's  SoftBank...

    • 8 Nov 2017
  • Breakfast Bytes: What's For Breakfast? Video Preview November 13th to 17th 2017

    Paul McLellan
    Paul McLellan

    https://youtu.be/Ar6PcH48DNo

     breakfast bytes logo

    Coming from David Intercontinental Tel Aviv (camera Natalie)

    Monday: CDNLive Israel

    Tuesday: Jasper User Group

    Wednesday: IEDM Preview

    Thursday: Arm TechCon Foundry Afternoon

    Friday: CASPA: AI and Semiconductor

    www...

    • 7 Nov 2017
  • Whiteboard Wednesdays: Whiteboard Wednesdays - A Practical Approach to Failure Modes, Effects, and Diagnostic Analysis (FMEDA)

    References4U
    References4U

    In this week's Whiteboard Wednesday, John MacLaren explains the steps required for Failure Modes, Effects, and Diagnostic Analysis (FMEDA) in automotive designs and the specific practices incorporated for Cadence DDR IP.

    https://youtu.be/ef-IuDKXf0E

    • 7 Nov 2017
  • Breakfast Bytes: October Revolution

    Paul McLellan
    Paul McLellan

    breakfast bytes logoToday is the 100th Anniversary of the October Revolution in Russia. But wait, isn't it November? Indeed it is, but back in 1917, Russia still had not switched from the Julian to the Gregorian calendar. Most European countries had done so a long time before...

    • 7 Nov 2017
  • Digital Design: Functional Correctness—The Forgotten Benefit of HLS

    dpursley
    dpursley

    I like to ask questions, because you learn a lot that way. In fact, I did a survey earlier this year and learned that high-level synthesis users’ experiences are exceeding the non-users’ expectations, and that HLS is being used for a wider variety of design types than even I knew. Recently I asked one of my favorite questions, and got an answer I truly didn’t expect.

    My favorite question to ask new HLS…

    • 6 Nov 2017
  • Breakfast Bytes: Tensilica Can Improve Your Image

    Paul McLellan
    Paul McLellan

    breakfast bytes logoWhy is image processing so important? To a first order approximation, all data is vision and video. Of course, things like GPS systems generate data too, but in terms of data volume the amount of data is trivial and the complexity of its processing is...

    • 6 Nov 2017
  • Analog/Custom Design: Art of Analog Design Part 7: Mismatch Tuning

    Art3
    Art3

    In days of future past, we looked at DC mismatch analysis and compared it to Monte Carlo analysis for analyzing the effect of device mismatch on the offset voltage of a differential amplifier. We found that DC mismatch does provide good estimates of the effect of mismatch with the limitation that the offset voltage has a Gaussian distribution. Since DC mismatch analysis only needed a single simulation to generate an estimate…

    • 3 Nov 2017
  • Breakfast Bytes: The Book That Changed Everything

    Paul McLellan
    Paul McLellan
    Academics have had a big influence on semiconductor design and design automation. I wrote earlier this week about Rob Rutenbar, the recipient of this year's Kaufman award, an academic as well as the founder of a couple of startups. Just a look at the...
    • 3 Nov 2017
  • Breakfast Bytes: CHIP: College Hire and Internship Program

    Paul McLellan
    Paul McLellan
    For some time, Cadence had an informal internship program: if managers wanted to hire an intern, then they could. But it was not formalized and it wasn't very consistent. As the Cadence Academic Network grew and went global, a few years ago we to...
    • 2 Nov 2017
  • Breakfast Bytes: What's For Breakfast? Video Preview November 6th to 10th 2017

    Paul McLellan
    Paul McLellan

    https://youtu.be/P3O79m4r-PM

    <

    Coming from the Cadence building 10 lobby (camera Sean)

    Monday: Embargoed release

    Tuesday: October Revolution

    Wednesday: Simon Segars: It's the Security Stupid

    Thursday: Social Engineering

    Friday: Arm's Security...

    • 1 Nov 2017
  • Breakfast Bytes: Cadence Academic Network Is Ten Years Old

    Paul McLellan
    Paul McLellan

    breakfast bytes logoPatrick HaspelYes, it's true, the Cadence Academic Network is having its tenth anniversary. The program is run by Patrick Haspel, who is now based in San Jose. However, he is from Mannheim in Germany, and when it started, the academic network was purely a European...

    • 1 Nov 2017
  • Whiteboard Wednesdays: Whiteboard Wednesdays - Understanding ISO 26262 Implications for Automotive Design Teams

    References4U
    References4U

    In this week's Whiteboard Wednesday, Anne Hughes explains the considerations for designs targeted at automotive applications and the impact of functional safety requirements on that process.

    https://youtu.be/wLMfGZk0u1I

    • 31 Oct 2017
  • Breakfast Bytes: Rob Rutenbar Is Recipient of 2017 Kaufman Award

    Paul McLellan
    Paul McLellan

      Ron RutenbarThis year's recipient of the Kaufman Award is Rob Rutenbar. He has a big connection to Cadence, since he was the founder of Neolinear, which we acquired in 2004. But there is a backstory of how Rob ended up in analog IC design in the first place. And...

    • 31 Oct 2017
  • Breakfast Bytes: October 2017 Breakfast Buffet

    Paul McLellan
    Paul McLellan

    https://youtu.be/2HhOBOftlv4

     breakfast bytes logo

    Coming from the roof of Cadence building 10 (camera Sean)

    CDNLive Taiwan Automotive Panel

    The Rise of the China IC Industry

    Linley Gwennap on the Microprocessor Market

    AMD's Early Experience with Portable Stimulus...

    • 31 Oct 2017
  • Analog/Custom Design: Simplifying the Memory Design Process

    Kim Khoury
    Kim Khoury

    On today’s SOC designs, the memory control logics and memory arrays take up a lot of real estate in terms of area and as a part of the larger system since it mostly determines the performance of the application. Regardless of the processors and the interconnect, the memory system provides the instructions and operands and the application cannot be executed any faster than the memory system can handle. Due to this…

    • 30 Oct 2017
  • Verification: Cadence and Arm Announce Early Access to Xcelium Parallel Logic Simulators on Arm-Based Servers

    XTeam
    XTeam

    On October 24, Cadence and Arm announced early access to the Xcelium Parallel Logic Simulation on Arm-based servers. It was demonstrated running on Cavium ThunderX2 and Qualcomm Centriq servers at the Arm Techcon event on October 25 and 26.  This represents a new development in low power, yet high performance simulation solutions for the EDA industry.

    Ensuring that designs function correctly is a huge challenge for the…

    • 30 Oct 2017
  • Breakfast Bytes: Andrew Kahng on the Last Semiconductor Scaling Levers

    Paul McLellan
    Paul McLellan

     breakfast bytes logo Andrew KahngIt's going to be academic week here on Breakfast Bytes. There is an anniversary coming up, the Kaufman award was announced recently, the Cadence Academic Network is having a birthday, and then there is the book that changed everything. So check in each...

    • 30 Oct 2017
  • Breakfast Bytes: Decoding Formal Club: Arm and Arteris

    Paul McLellan
    Paul McLellan

     breakfast bytes logoAt the latest meeting of the Decoding Formal Club, organized by Oski and sponsored by Cadence, the agenda promised three things:

    • Lessons Learnt from a Deployment of Sign-Off Formal on a High-Performance Arm CPU, by Vikram Khosa, formal verification...
    • 27 Oct 2017
  • System, PCB, & Package Design : SI Methodology for Multi-Gigabit Serial Link Interfaces (2 of 8)

    Sigrity
    Sigrity
    Let’s assume that we are working on a PCI Express Gen 4 serial link, running at 16Gbps. Let’s also assume that we were able to obtain models for the AC coupling caps, packages, and connectors from your suppliers, as well as an IBIS-AMI mo...
    • 26 Oct 2017
<>
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