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Latest Blog Posts

  • Verification: The DWARF Debugging File Format

    jasona
    jasona
    The Chronicles of Narnia has always been one my favorite series of books. Today, I'm not going to talk about dwarfs such as Trumpkin, the dwarf that appeared in Prince Caspian (check out the latest movie), but instead something called the DWARF D...
    • 12 Jun 2009
  • Verification: Enabling OVM Transaction Debug in SimVision Without Code Changes

    Team genIES
    Team genIES
    Are you tired of putting print statements in your code to do debug?  Do you work with designers who just want to use waveforms to debug testbench and design problems?   

    There is a cool feature in the OVM library and Incisive Enterprise Simulator that comes to the rescue.  It is the built-in OVM transaction recording.

    Modern metric driven testbenches generate a lot of dynamic data on the fly during a simulation…

    • 11 Jun 2009
  • Verification: Team genIES Bloggers Create Simulation Magic

    Team genIES
    Team genIES

    Simulation is a huge topic.  Performance, debug, mixed-signal, low-power, assertions, coverage, IEEE languages, lint checking, interfaces, and much more.  Many of us started using simulation when it was gates and waveforms while others joined in the era of complex, multi-language, testbench-driven simulation. Regardless, the pace of design and verification is accellerating for all of us.  So how can we get those pearls of…

    • 11 Jun 2009
  • Verification: Tips on Using “vhdlsync” With e+Mixed HDL Simulation

    teamspecman
    teamspecman

    [Team Specman welcomes Principal Support Application Engineer Avi Farjoun to share some important tips on the famous “vhdlsync” switch]

    As users with mixed VHDL and Verilog environments know, even in this day & age mixed HDL simulation cycle semantics are not very well defined.  Even worse: there is no standard that specifies the order of execution of always blocks and VHDL processes, which can lead to simulation…

    • 11 Jun 2009
  • Verification: Thoughts on the DVClub Talk: "Is it Time to Declare Verification War?"

    jvh3
    jvh3

    As noted in a prior post, I had the pleasure of attending a DVClub talk given by Brian Bailey entitled "Is it time to declare verification war?". As suggested by the word "war" title, Brian drew many analogies between the legendary text The Art of War by the Chinese general Sun Tzu, and the strategic and tactical challenges of verifying a complex device under test (DUT), complemented by introductions…

    • 10 Jun 2009
  • Analog/Custom Design: Things You Didn't Know About Virtuoso: Managing Your Real Estate - Part 1

    stacyw
    stacyw

    Yeah, right...in this economy, don't talk to me about real estate.  But I'm not talking about home prices, I'm talking about that territory on the screen right in front of you where you spend your day drawing and clicking and arranging and rearranging in order to accomplish your job.  Cadence has given you lots of tools to help you develop your little plot of land.  Just recently in this blog, I've told you about…

    • 9 Jun 2009
  • Verification: Heads-up: Mixed Signal Verification Webinar (June 10)

    teamspecman
    teamspecman

    For those Specmaniacs using the REAL number data type & ports capabilities in Specman, you might be interested in a webinar our analog colleagues are hosting tomorrow (June 10) from 07:00- 8:15 AM (PDT) and a second broadcast at 10:00 -11:15 AM (PDT).  Specifically, the webinar is titled "How to Boost Performance for Mixed Signal SoC Top-level Verification", and it will address how to handle mixed signal design…

    • 8 Jun 2009
  • RF Engineering: Join us at the Cadence booth at the International Microwave Symposium

    Hany
    Hany

    If you listened to Tom's advice on this blog two months ago and registered for the International Microwave Symposium or the RFIC symposium, then you should be at the Boston Convention center now enjoying RFIC talks. Please remember that we are waiting...

    • 8 Jun 2009
  • Verification: New IntelliGen Statistics Collection Utilility

    teamspecman
    teamspecman

    As noted in white papers, prior posts, and the Specman documentation, since IntelliGen is a totally new stimulus generator than the original "PGEN", there is usually some amount of effort needed to migrate an existing verification environment to fully leverage the power of IntelliGen.  To help expedite this process, I've just posted in the Community's Shared Code area a simple utility that allows you to…

    • 5 Jun 2009
  • Verification: Synthesis Really DOES Need to Change

    archive
    archive
    A great article appeared in Chip Design a few weeks ago written by Tets Maniwa, “Synthesis Needs to Change to Serve Modern Chip Design”. Tets Maniwa is sharp guy. (Those of you designing ICs in the mid/late 1990s probably r...
    • 2 Jun 2009
  • Analog/Custom Design: Things You Didn't Know About Virtuoso: Editing Properties

    stacyw
    stacyw

    When I was growing up, my mother would usually bake a ham for Christmas dinner.  She would always cut a slice off the side before putting it in the pan to cook.  One day I asked her why she did this and she replied that her mother always did it that way.  Now, I've never been the type of person who easily goes along with the "because we've always done it that way" kind of answer, so I asked my grandmother the same question…

    • 1 Jun 2009
  • Digital Design: MarCom 2009 - New, Exciting, Educational

    archive
    archive

    As a Marketing Communications professional, I am always looking for creative ways to communicate with our current and potential customers. Over the last 13 years that I have been in this profession, I have seen many methods and vehicles used by Cadence and various other companies to reach out to external and internal audiences. I must say that some of the things I have seen have been pretty creative and unique. Last year…

    • 29 May 2009
  • SoC and IP: The Great Escape, Part II: How These Companies Exited the DRAM Business

    Denali Blog
    Denali Blog
    Case Histories of Significant DRAM Market Withdrawals:

    This article continues our earlier discussion about the same topic from last week, entitled "...Part I."

    It includes highlights of the most significant departures from the DRAM business over the past two decades, and describes, in broad terms, the experience of these DRAM makers in the market, historically and the events that led to their departures. In some…
    • 28 May 2009
  • Verification: Inside Cadence: "Stars & Strikes" charity event

    jvh3
    jvh3

    Allow me to make a brief digression from EDA technology blogging to give you all a peak at what goes on inside of Cadence.  Specifically, last Thursday May 21 here at the Cadence San Jose campus we had a welcome break in our daily routines for a good cause -- the annual "Stars & Strikes" charity festival.  Let me explain: each year, Cadence offices around the world adopt a single, local charity to be the focus…

    • 28 May 2009
  • Verification: Where's the Bridge to Cross the Great Divide?

    jasona
    jasona
    At this year's Embedded System Conference in San Jose there was a panel with the title Who's Taking over Whom - Is EDA Moving into Embedded or Embedded into EDA?One of the analogies Mike McNamara from Cadence used was hardware and software en...
    • 28 May 2009
  • Verification: New "E" text editor and e templates

    teamspecman
    teamspecman

    Imagine Team Specman's surprise when we came across this article on Slashdot about "the new E text editor":
    http://tech.slashdot.org/article.pl?sid=09/03/24/172202

    This was the first we've heard of this product, and we're curious to find out how the author came up with the name "E".  Anyone, anyone ....?

    Regardless, since Cadence in general, and Specman and Incisive Enterprise Simulator-XL

    …
    • 27 May 2009
  • SoC and IP: Denali MemCon leads "Memory Week" in Silicon Valley, June 22-25

    Denali Blog
    Denali Blog
    Denali MemCon 2009, scheduled for the Santa Clara Hyatt Regency on June 22-24, is a great opportunity to gain insight into the latest trends in the memory products, markets and technologies.

    The week kicks off on Monday, June 22, when Denali hosts a full day of training and tutorials on their Databahn DDR3 contoller, their Industry Leading MMAV memory modeling and verification products, High speed NAND design, PCIe…
    • 26 May 2009
  • Analog/Custom Design: Things You Didn't Know About Virtuoso: Navigator Assistant

    stacyw
    stacyw

    Have you ever found yourself working with a massive schematic having to constantly zoom and pan around to find the block you're looking for (since they all look alike from high altitude)?  Then you descend into the block only to find that the sub-block you really wanted is somewhere else?  Well, pop back up and start over again...

    Have you ever run a simulation which finds a problem with transistor I44.I23.I0.I25.NM2?  Again…

    • 26 May 2009
  • SoC and IP: The Great Escape, Part I: How These Companies Exited the DRAM Business

    Denali Blog
    Denali Blog
    Updated version to reflect correction to company naming due to errors in original (5/28/09)

    Today's Memory Market is the Toughest Ever.

    The memory marketplace has always invited participation and competition since the earliest beginnings of the semiconductor business in the 1970s. Needless to say, with the memory supplier base becoming more and more concentrated, most of those once-participants no longer make…
    • 22 May 2009
  • Verification: Report from CDNLive! EMEA 2009

    tomacadence
    tomacadence

    CDNLive! in Munich had it all - stimulating customer papers, demonstrations of new Cadence solutions, lots of lively technical interaction, even dancers in the exhibition hall and a funk band at the evening party. Given customer travel restrictions, there were fewer attendees from the more distant areas of Europe, but many sessions were packed and the common areas were busy. I attended most of the sessions in the Functional…

    • 21 May 2009
  • Verification: Tech Tip: Weighting Generation of "Extreme" Values

    teamspecman
    teamspecman

    [Team Specman welcomes guest blogger Vitaly Lagoon, an Architect in the Generation Technology R&D group]

    Consider the case where you have a generatable variable "x" taking random values from [0..99], i.e. all values are declared equal from the generation point of view.  However, imagine that from a verification perspective you are most interested in checking the extreme cases x==0 and x==99, as well…

    • 21 May 2009
  • Verification: Heads-up: DVClub Boston Coming Up On June 1

    jvh3
    jvh3

    Back on March 19 here in Silicon Valley, verification guru Brian Bailey gave a great talk at DVClub entitled "Is it time to declare verification war?". Brian had some interesting insights as usual, prompting me to start to write a blog post about it. However, some business and personal events intervened, and in the interim Brian scheduled an encore performance of his talk at the Boston area DVClub meeting this…

    • 20 May 2009
  • SoC and IP: Memory Company Financials, 1Q09

    Denali Blog
    Denali Blog
    1Q09 Better than 4Q08, but still terrible:
    Memory makers continued to suffer horrendous losses in 1Q09, effectively wrapping about $1.75 around each of the 4B or so units of DRAM, NOR and NAND that they shipped to end customers during the quarter. According to our compilation of memory makers' 1Q09 results, they collectively lost about $6.7B on sales of $9.3B. (The "losses narrow at Elpida, Hynix and Micron" headlines…
    • 19 May 2009
  • Analog/Custom Design: Things You Didn't Know About Virtuoso: Tabs and Bookmarks

    stacyw
    stacyw

    Do you remember the first time you used a browser with tabs?  All of a sudden, there you were...surfing two, three, four websites at once in the same window.  Yee-haw!  Life is good.  Well, now you can do the same thing in Virtuoso.  Okay, so you can't put YouTube in one tab and your schematic in another (yet), but you can easily have multiple tabs with schematics, layouts, symbols, etc. all in the same window. 

    No more minimizing…

    • 19 May 2009
  • Verification: Way Worse Than The Real Thing

    TeamESL
    TeamESL
    This week Cadence and Virtutech announced a collaborative effort to bring together the Virtutech Simics virtual platform with the Cadence ISX software testing system. This is a very interesting combination of technologies, clearly demonstrating ho...
    • 18 May 2009
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