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Latest Blog Posts

  • SoC and IP: Chip Dis-integration

    TomWong
    TomWong

    I was asked the following question recently.

    No longer are we seeing increasing amounts of functionality being crammed into chips, except under very special circumstances. Chips today are trending towards the leaner side. Is this only when power is a primary concern? Does this apply to all technology nodes or only to larger ones? What about pins – I/O has often been the limiter. What impact will this have on IP? Will…

    • 27 Jun 2018
  • Breakfast Bytes: DAC Tuesday: IBM's AI, Jay's Wall Street View, Lip-Bu's Chat, Monster Chips

    Paul McLellan
    Paul McLellan
    The second day of DAC needed several clones of me at lunchtime. Lip-Bu Tan's turn in the DAC pavilion overlapped with the digital lunch, which overlapped with a presentation by DARPA on silicon compilers, and a Cadence panel on cloud in the Cloud...
    • 27 Jun 2018
  • Whiteboard Wednesdays: Whiteboard Wednesdays - Introduction to Functional Safety From an IP Supplier

    References4U
    References4U

    In this weeks Whiteboard Wednesdays Divya Kalimuthu speaks about ISO 26262 from the perspective of a Safety Engineer. She speaks about how the standard is applied in various levels of a supply chain.

    www.youtube.com/watch

    • 26 Jun 2018
  • The India Circuit: The New India: Rise Of The Cashless Wallets

    Madhavi Rao
    Madhavi Rao
    Can India really ever go cashless? This was one of the topics that was discussed at a talk organized recently at Cadence in which we had invited Bhaktha Keshavachar, CTO and Co-Founder of Ezetap Mobile Solutions, to talk to Cadence employees about pa...
    • 26 Jun 2018
  • Breakfast Bytes: DAC Monday: Amazon's Things, Handel's Megadesign, Cooley's Troublemakers

    Paul McLellan
    Paul McLellan
    Another year, and another DAC. As usual, the proceedings kicked off on Sunday night with the welcome reception, and that went straight on to the Heart of Technology (HOT) party, raising money for the Gary Smith Memorial Scholarship at SJSU. Lori Kate...
    • 26 Jun 2018
  • System, PCB, & Package Design : Improve Your Circuit Manufacturing Yield with Monte Carlo Analysis in PSpice

    Ronak Shah
    Ronak Shah
    Generic Spice Technology is past. Let me introduce you to the powerful Monte Carlo process in today's PSpice Advanced Analysis
    • 25 Jun 2018
  • Breakfast Bytes: Cadence Cloud

    Paul McLellan
    Paul McLellan
    Today Cadence announced Cadence Cloud. This is the beginning of a major change in how EDA capabilities are delivered. I doubt that all EDA will move into the cloud—there will certainly be some customers who want to keep some of their computatio...
    • 25 Jun 2018
  • Breakfast Bytes: Remember Virtual CAD? DesignSphere Access? What an ASP Was?

    Paul McLellan
    Paul McLellan
    Last time I worked for Cadence in the early 2000s, Adriaan Ligtenberg ran methodology services and, in particular, something we called Virtual CAD. The idea of Virtual CAD was to allow companies to outsource their CAD group to Cadence. In effect, we...
    • 22 Jun 2018
  • Verification: Is It Time to Verify Your Chips in the Cloud? Part 2 of 3

    XTeam
    XTeam

    Welcome back to our series on cloud verification solutions. This is part two of a three-part blog—you can read part one here.

    The high-performance computing (HPC) market continues to grow. Analysts say that the HPC market will reach almost $11 billion by 2020—that’s an annual growth rate of almost 20%. Cloud providers and other related companies are putting more and more resources into building solutions for this…

    • 21 Jun 2018
  • Verification: App Note Spotlight: Streamline Your SystemVerilog Code, Part III - SystemVerilog Data Structures

    XTeam
    XTeam

    Welcome back to the third installment of a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked—Simulation Performance Coding Guidelines for SystemVerilog. This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t specific to just…

    • 21 Jun 2018
  • Breakfast Bytes: Automobil Elektronik Kongress 2018

    Paul McLellan
    Paul McLellan
    Once a year for 22 years the electronic divisions of the European automotive industry converge on the small town of Ludwigsburg just outside Stuttgart. Stuttgart is a big enough city, you've probably heard of it. In the automotive world, it is home t...
    • 21 Jun 2018
  • Breakfast Bytes: What's For Breakfast? Video Preview June 25th to 29th 2018

    Paul McLellan
    Paul McLellan
    https://youtu.be/-fwwmFE6yUs Coming from Automotiv Elektronik Kongress (camera Robert Schweiger) Monday: Embargoed Tuesday: DAC day 1 Wednesday: DAC day 2 Thursday: DAC day 3 Friday: Embargoed www.breakfastbytes.co...
    • 20 Jun 2018
  • Breakfast Bytes: Movie Theater Sound in Your Phone

    Paul McLellan
    Paul McLellan
    Dolby Atmos is immersive sound. As Dolby puts it: Dolby transports you into the story with moving audio that flows all around you with breathtaking realism Well, there is some level of colorful marketing there, but it really does have to be heard t...
    • 20 Jun 2018
  • Whiteboard Wednesdays: Whiteboard Wednesdays - Introduction to ADAS  with a Real-Life Example

    References4U
    References4U

    In this week’s Whiteboard Wednesdays video, Marc Greenberg, walks us through a typical ADAS system architecture and then provides a real-life testimonial on the value of these systems.

    https://youtu.be/EQL4jeD25_g

    • 19 Jun 2018
  • Breakfast Bytes: RSA Wrapup: Song, Darling, Thrun

    Paul McLellan
    Paul McLellan
    The closing session of the RSA conference was a sort of chat-show hosted by Hugh Thompson, who is the RSA Program Chair. He brought up three people, two of who have featured in Breakfast Bytes posts before. The proceedings started with a session wher...
    • 19 Jun 2018
  • Analog/Custom Design: Virtuoso Video Diary: What's this Net Connected to?

    sarahfino
    sarahfino
    Meet the Virtuoso Schematic Editor L Probes assistant, a dockable assistant where you can identify connections that exist for a net, filter on these connections and save the probe path information to a CSV file.
    • 19 Jun 2018
  • Breakfast Bytes: Why Millennial Engineers Should Work for Cadence

    Paul McLellan
    Paul McLellan
    Many years ago, when Nokia was at the top of its game—one in every three phones shipped was a Nokia—I chatted to the sister of a friend of mine who was something senior in Nokia finance. I think she was the controller for a good part of t...
    • 18 Jun 2018
  • Academic Network: Academic Track at CDNLive EMEA 2018

    Anton Klotz
    Anton Klotz
    From 7-9.05 the CDNLive circus made it stop in Munich / Germany for full three days. For Academic Network in EMEA this is the most important event through the year, as we are organizing the Academic Track and invite our academic partners to attend, p...
    • 17 Jun 2018
  • Verification: Is it Time to Verify Your Chips in the Cloud? Part 1 of 3

    XTeam
    XTeam

    Welcome to the first installment of a three-part blog series examining the issues and opportunities for performing verification in the cloud.

    For a while now, there’s been a growing interest in cloud-based EDA solutions, but the time wasn’t ripe for production deployment. People had concerns about security and the sustainability of the data centers. But nowadays, public clouds are highly secure, typically more secure…

    • 15 Jun 2018
  • Breakfast Bytes: The Design Infrastructure Alley

    Paul McLellan
    Paul McLellan
    One of the new things at DAC this year is the Design Infrastructure Alley.  The Alley is an initiative from the ESD Alliance and the Association for High-Performance Computing Professionals to highlight the information technology infrastructure,...
    • 15 Jun 2018
  • Breakfast Bytes: Pie and Chips at DAC: ChipEstimate.com and the First Annual Pi Contest

    Paul McLellan
    Paul McLellan
    In Scotland, there is a traditional dish of pie and chips. But the pie is not a sweet fruit pie, like something Marie Callendar would make, but it is full of minced lamb. And chips are what Americans call fries (except in the phrase "fish & ...
    • 14 Jun 2018
  • System, PCB, & Package Design : What Is COM /JCOM Channel Compliance All About?

    Sigrity
    Sigrity
    In today’s world of double-digit gigabit-per-second data rates it is imperative that engineers properly design and characterize their system to meet standards compliance.  This sounds simple enough but actually simulating a high-speed ser...
    • 13 Jun 2018
  • Breakfast Bytes: "I Couldn't Imagine Being Too Poor for Servants, or Rich Enough for a Car"

    Paul McLellan
    Paul McLellan
    Agatha Christie, looking back on her early life, remarked that she: I couldn’t imagine being too poor to afford servants, nor so rich as to be able to afford a car. Like most of us, I've been the other way around. I've owned a car sin...
    • 13 Jun 2018
  • Whiteboard Wednesdays: Whiteboard Wednesdays - What Really Matters When Selecting IP

    References4U
    References4U

    In this week’s Whiteboard Wednesday, Tom Hackett says that PPA is only the tip of the iceberg of requirements to consider when selecting IP for your next chip design.

    https://youtu.be/2S6V5RpXECM

    • 12 Jun 2018
  • Digital Design: High-Level Synthesis: The Secret Is Out

    dpursley
    dpursley

    cdnliveGone is the day when companies (our customers) kept their use of high-level synthesis (HLS) quiet, a secret advantage over their competitors. As HLS usage became more widespread, the secret is out, and now the HLS community is talking and sharing experiences with each other.

    Take CDNLive, for instance. This year, HLS discussions are happening at the CDNLive shows worldwide. Since it’s extremely unlikely any of you have…

    • 12 Jun 2018
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