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The recent embedded neural network symposium held at Cadence wrapped up with a panel session. Chris Rowen was the moderator and I think the panelists were Han Song, Ren Wu, Forest Iandola, Kai Yu and Jeff Bier (who all presented earlier...

In addition to being the master of ceremonies for the recent embedded neural network symposium, Chris Rowen also presented his own thoughts. Chris used to be the CTO of Tensilica, and after Cadence acquired them he became the CTO of the IP group. Last...

The keynote at the recent Embedded Neural Network Symposium held recently at Cadence was given by Kunle Olukotun who is a professor at Stanford sponsored by Cadence. His keynote was titled Scaling Machine Learning Performance with Moore's Law. He...

In this week's Whiteboard Wednesdays video, Nimrod Reiss discusses the challenges of verifying a coherent interconnect such as snoop filtering, throughput and latency, and dealing with third-party interconnects.

www.youtube.com/watch

Jeff Bier is the founder of the Embedded Vision Alliance, which runs the annual Embedded Vision Summit (and other things). You won't be surprised to learn that his talk at the Embedded Neural Network Seminar was on embedded vision, titled When Every...

Cadence Academic Network recently participated in the 2016 IEEE and CEDA Workshop on Electronic Design Automation (EDA) in Taipei. The event attracted over 200 attendees from academia.  This workshop was a unique opportunity for Cadence users to share...

https://youtu.be/EVZ4T8TPim8

Coming from inside a Microsoft Hololens

Monday: High Speed Parallel Simulation

Tuesday: Embargoed release tied to SPIE Advanced Lithography

Wednesday: Embargoed release tied to Mobile World Congress (MWC)

Thursday...

Have you ever plotted an eye diagram in Virtuoso Visualization and Analysis XL and wished that you could overlay an industry standard eye mask to see if your diagram is compliant? Well, now you can! The new tab, Eye Mask, in the Eye Diagram assistant helps you apply a mask from the following industry standards:

• HDMI Compliance
• HDMI 2.0 TP2EQ (Data Rate 3.4G to 3.712G)
• HDMI 2.0 TP2EQ (Data Rate 5.9G to 6G)
• MIPI…

A couple of weeks ago, Cadence held the second embedded neural network symposium (ENNS). Neural networks are a hot topic. In fact, this was the biggest event ever held on the Cadence campus with over 300 people registered (I think around 200 showed up...

For most chips, the automatic routing in Innovus—NanoRoute—works well. But there are certain styles of chips that are more challenging for a grid-based router to do clean structured routing.

• Large die size designs with buses that go from...

One of the perks of writing this blog is that I get offered review copies of interesting books related to the semiconductor industry. It is hard to go a day without hearing about IoT security issues (and I write about it regularly, most recently in Video...

Tom Quan recently came to Cadence to talk about TSMC's automotive strategy. Tom and I go back a long way since fifteen years ago, when I was running the custom IC group. I hired him into Cadence to work for me to run a project that had the nickname Superchip...

https://youtu.be/HL0GFG9tNP4

Coming from Cadence security camera

Monday: Embedded Neural Network Seminar Summary

Tuesday: Jeff Bier, When All Devices Can See

Wednesday: Kunle Olukotun, Scaling Machine Learning

Thursday: Chris Rowen, ENN the New...

In this week's Whiteboard Wednesdays video, principal AE Matt Diehl explains how predefined callback functions in the Cadence VIP agents enable error injection, print logging, event triggering, and scoreboarding in UVM testbenches.  A DisplayPort VIP example is shown, which illustrates the quick and easy scoreboarding method.

Yesterday I wrote a post He Who Goes First...Loses about how being first isn't always a good thing. Either in the short term, being first is a negative, or there is a short-term positive but longer term things are not so great.

There is a saying, of course, that he who goes first wins. And sometimes, and in some ways, that is true. But not always, and especially not always in the long run.

The most obvious example of going first being dangerous is the forlorn...

Igor Keller gave an internal presentation on Handling Variability in the Modern Design Cycle last week. He is one of the key architects for the Tempus timing engine. However, since his presentation was mostly about the state of the art in static timing...

https://youtu.be/XOS4sfILahc

Coming from Design Con 2017

Monday: He Who Goes First...Loses

Tuesday: He Who Goes First Loses, EDA Edition

Wednesday: TSMC Automotive Strategy

Thursday: Book on Circuits and Systems for Security and Privacy

Friday...

Congratulations to the IEEE-1647 e Functional Verification Language Working Group (eWG)

In the beginning of 2017, the IEEE-1647 eWG issued for publication IEEE Std 1647™ 2016, IEEE Standard for the Functional Verification Language e. This version of the standard, issued under the chairmanship of Darren Galpin from Infineon, with input from other members from the EDA industry, contains enhancements of the e language…

One of the first posts I wrote here at Breakfast Bytes was Where Does 5 Really Mean 30? about process node naming. One company that is heavily involved with process nodes is ASML, and they have attempted to standardize nomenclature to a "standard node...

At the no-longer-so-recent Jasper User Group JUG last year, the keynote was by Erik Seligman. He is one of three authors, along with Tom Schubert and the very nautically named MV Achutha Kiran Kumar (MV stands for motor vessel and is used in front of...

In this week's Whiteboard Wednesdays, Scott Jacobson wraps up his three-part series on Ethernet by focusing on what Ethernet is like today, and how it has expanded into applications like automotive and industrial control.

https://youtu.be/KdOS1SECj90

There are lots of claims to be the first computer, depending on your definition of "computer". Babbage's difference engine was clearly a computer of sorts, although not electronic. His analytical engine was even programmable. But it was finally completed...

Creating a neat and organized schematic is extremely important, and often requires a great deal of forward planning and effort. Placing, aligning, and distributing objects can be time-consuming, if performed manually. However, improvements to the Cadence Virtuoso Schematic Editor accelerates and simplifies this design entry process. New Align and Distribute options simplify placing the objects in a more systematic manner…