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Web applications for electronics design provide an environment where users can apply their knowledge, and thus accelerate learning. These virtual laboratories provide plenty instruments and pre-built circuits or systems, that enable users to do experiments...

In this week's Whiteboard Wednesdays video, James David talks about the benefits of two types of error injection, predefined and callbacks.

https://youtu.be/BhTdY9fkF70

With cloud technology going vertical, everything is changing. The world is connected like never before—managing and processing large amount of data, every single second. Augmented/Virtual Reality is the latest game changer, even in its early stage of development and proliferation. The gathering of semiconductor experts at CDNLive Israel confirmed these and other trends are impacting everything from IP to tools to business…

Yesterday, I wrote about the new 12FDX process, which is a derivative of the original 28nm FD-SOI process developed by ST Microelectronics. Last year I talked to Thomas Skotnicki. He is the father of thin-box FD-SOI and its birth is an interesting story...

We are not talking about how your design compares to the next guys’, we’re talking about the PCB layer structure of your design, be it rigid, flex, rigid-flex, or using inlay technology. Stackup definition, more specifically accurate stackup definition, is critical for a wide variety of reasons. The arrangement of the various materials affect the computations and analysis for controlled impedance nets and…

The Story So Far

GLOBALFOUNDRIES had a 28nm Hi-K PolySi process. I think that even they would admit that they were late to market with it. They also announced that they were licensing 28nm FD-SOI from ST Microelectronics who developed it, and I think...

In this new age of complex designs and scaling of technology nodes, there are more number of wires per given square unit of area. As a result, applying constraints is considered wise to make sure signal integrity (SI) is taken care off well. It is due to this reason that circuit designers show a growing preference for using a larger number of constrained and managed nets. These constrained nets, if possible, can be used…

At the recent MIPI DevCon, Cadence's Ofir Michaeli gave two presentations on verification. The first was Effective Vertification of Stacked and Layered Protocols. Then he was back later in the day to cover Using MIPI Conformance Test Suites for Pre...

https://youtu.be/P3jRt2HEe8U

Monday: GLOBALFOUNDRIES announced new nodes on their process roadmap. I take a look.

Tuesday: One of the new GF processes is 12FDX, an FD-SOI process. Last year I interviewed Thomas Skotnicki about how he came from Poland...

MemCon, the annual all-things-memory conference originally started by Denali and since continued under the Cadence umbrella, took place at the Santa Clara Convention Center this past Tuesday.

The morning started with two keynotes, the first by Hugh Durdan...

The 17.2 Allegro PCB Editor has improved backdrill capabilities.

Backdrill data is now stored in the library padstacks and utilized at the design level during the analysis and backdrill generation process. Padstacks which do not have pre-defined backdrill...

You hear a lot about cache coherency these days. In fact, at the recent Linley processor conference, no fewer than three companies announced new cache-coherent networks-on-chip (NoCs).

The first cache I ever ran into was on a computer at Cambridge...

In this week's Whiteboard Wednesdays video, the second in a two-part series, Lana Chan explores the factors that drove the development of PCIe Gen4. She also details SoC concerns that design and verification engineers need to address in their designs.

https://youtu.be/4FSZ432fqG4

Countries which were founded after the collapse of Yugoslavia have long tradition in microelectronics. Due to import limitation during the time of Iron Curtain, Yugoslavians had to be inventive. As a bloc-free country they still had access to Western...

At the Linley Processor conference recently, there was a presentation about RISC-V from Krste Asanović, who is the leader of the team that defined the RISC-V ISA at UC Berkeley, and is currently on leave of absence working full-time at SiFive, a company...

DVCon Europe in Munich is coming up on 19 and 20 October. For any Americans reading this and thinking October in Munich means Oktoberfest and beer, I hate to disappoint you. Despite the name, Oktoberfest is largely in September (it ends on the first Sunday...

Increasingly, taking an appropriate ARM^® processor has become the standard way to pipe-clean a digital flow in a new process. ARM processors are widely used and are available at various levels of complexity. For 10nm (what TSMC calls N10), Cadence...

https://youtu.be/Ej7aa83-OFM

Monday: A preview of DVCon Europe on 19th/20th October, where Cadence is presenting 3 tutorials and several papers.

Tuesday: At the Linley Processor Conference, Krste Asanović presnted the RISC-V ISA and then Markus Levy...

I had an interesting conversation with Michiel Ligthart and Rick Carlson of Verific. They have a unique niche in the EDA ecosystem. They provide parsers for SystemVerilog, VHDL, and IEEE 1801 (fka UPF). They really have no competition other than companies...

“Finland is not Scandinavia” was one of the first statements I heard, when I landed in Norway.

“OK, let's consider it as a Nordic country”, I said, trying to resolve the situation.

“Nordic is fine”.

So Denmark...

When I first started programming, the first programming language I learned was Fortran IV. In that era, learning to program at that age was rare, since the only computers that existed were mainframes. This was before the minicomputer, let alone the various...

To address the growing needs for floating-point arithmetic in DSP algorithms, all Tensilica DSP families support floating point. In this second part of a two-part Whiteboard Wednesdays video series, we discuss the scalable floating-point capabilities across Tensilica DSP families that provide developers with the most choice for their application.

https://youtu.be/oTdzedEkVg0

The best way to complete a complex task is to break it into smaller, simpler tasks.

This is exactly what Symbolic Placement of Devices, popularly known as SPD, does for layout engineers. SPD is a symbolic row-based placer. Designed primarily for small to medium-sized designs, SPD displays only the relevant information needed to perform device placement. Using SPD layout, engineers can easily edit device placement…