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No doubt by now you have heard about the Innovus Implementation System, our next-generation physical implementation solution. It's always a bit scary to move to a new tool, but let me assure you that if you are a current Encounter user, you will be able to get around just fine in the Innovus system. A lot of the user interface will look very familiar to you, but there are some important changes and improvements…

I attend IEEE 802.3 Ethernet standards meetings and blog about them from time to time. (For past blog posts, see the list at the bottom of this post).

The most recent 802.3 meeting was held in Pittsburgh and has just finished. Pittsburgh is very interesting with fine buildings and nice parks. It sits at the confluence of two wide rivers and was a major transportation and steel town in its day. I've included some photographs…

In the previous blog post, we created a simple multi-language verification environment, running UVCs implemented in SystemVerilog and in e.

The architecture of the environment is as pictured here:

We will now add to this environment a system-level checker, implemented in SystemVerilog.

A standard recommended way for passing items is via TLM ports. For connecting ports instantiated within components implemented in…

Seems that by now, every one in the industry realizes that multi-language verification environments are not a faraway vision, something only for eccentric verification experts. Multi-language is here, simply because we need it.

Because there is no sense in throwing away a high-quality verification environment just because someone else prefers coding in a different language. Because there is no sense in forcing engineers…

This blog starts with a description of a debugging session of a mysterious behavior we encountered. Unlike a good mystery book, I will tell you upfront who did it—deep_copy(). In the second part of the blog, we’ll recap e’s copying methods, and we’ll understand how to avoid such mischief.

The mystery started when we saw that, in one verification environment, a struct that was expected to perform…

With the USB protocol being so popular nowadays (and frankly speaking, was there ever a time it wasn’t?), there are many advantages of enabling USB in an application, like versatility, ease of use, proliferation within the industry. However, there are also some hidden potential traps, which I'll discuss in more detail here.

USB design IP has…

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty continues his discussion on DDR4, with a focus here on bank grouping of DDR4.

https://youtu.be/_4lWfP5eDcQ

Most of our customers use the product documentation, Help, and Cadence Online Support capabilities while using our products and flows. There is a team working on developing the next generation of Cadence documentation and the Help utility.

The Cadence Online Support - Cadence Support News area recently posted the following:
“Cadence is committed to providing high-quality documentation. To help us shape the future of Cadence…

Think that DAC is all about EDA tools? Not anymore. This year there are over 100 presentations in the IP track, plus other sessions that are all about IP. After all, it’s almost impossible to find a chip design these days that doesn’t employ some type of IP.

Come see many of us from the IP Group at Cadence at DAC, June 7 – 11, at Moscone Center in San Francisco. You can’t miss the Cadence booth—we’re…

I’ll never forget covering a presentation that then-National Semiconductor CEO Brian Halla gave about a dozen years ago.

He talked of a time when electronics would be everywhere, taking in the analog world and converting that intake into useful data. In those post-911 days, he envisioned remote and even flying security cameras around structures like the Golden Gate Bridge. It was before drones took off and before…

1. Spectre PSPICE Netlist Support

Spectre technology enables the user to include PCB components in PSPICE format into a Spectre integrated circuit simulation. The solution is based on the approach of using a regular Spectre simulation including the Spectre simulator control statements, but additionally allowing inclusion of user-defined sub-circuits in PSPICE format.

2. Setting Up Liberate MX for…

In this week's Whiteboard Wednesdays video, Jacek Duda explains the implications that the Type C Connector has on the USB On-the-Go Controller.

In the 16.6 Allegro PCB Editor release, net associations to split planes are now stored in the database. This reduces chance of error when re-generating split planes on positive or negative layers. The former use model required re-assignment of a net during the command, which was error prone and cumbersome.

When a split plane is regenerated, the net choice dialog for each shape is set to the default net that will be assigned…

In this week's Whiteboard Wednesdays video, Lou Ternullo reviews the latest DRAM innovations and how they help improve density at the system level.

Nothing beats knowing, a late electronics-industry veteran used to say. That’s no more crucial than in debug, where Cadence has recently rolled out the new Indago Debug Platform to attack the biggest bottleneck in the IC functional verification flow.

Richard Goering, who blogged about the announcement, wrote: “Part of the Cadence System Development Suite, the Indago Debug Platform can reduce the time to identify…

In this week's Whiteboard Wednesdays video, Susan Peterson breaks down why you should buy memory models from Cadence versus getting them from manufacturers.

https://youtu.be/rlttauMzFEI

Hear what Bruce Imai—a Cadence Educational Services course developer—Cadence Application Engineers, and customers have to say about the valuable content available in our Allegro Design Entry HDL Front to Back Flow Cadence Training course. As Bruce emphasizes, “You’ll learn in a short amount of time techniques that might take you months to discover yourself.”

Here’s the video:
https…

USB is regarded as the world’s most popular serial interface, with over 1 billion devices shipping every year. This means there are a lot of players in the market, and many possible applications. From mice to mobile application processors, through set-top boxes and video cameras, it’s actually hard to imagine a device that is not USB-connected. How then should a designer make a decision today, that will not make his product…

In this week's Whiteboard Wednesdays video, Bob Salem takes a closer look at analog front-end interfaces and why they are important for the wireless communications market.

https://youtu.be/UJMXrTCu4IY

In this week’s Whiteboard Wednesdays, Chris Rowen highlights the requirements of the wide variety of sensors – environmental, motion, audio, and imaging. He'll cover data rates, sample rates, and levels of computation associated with sensors. He'll also discuss why, since computational requirements vary so much, a new DSP is needed. The Tensilica Fusion DSP uses a very flexible architecture that can be tailored for the…

The suppression of unassigned indirect vias is now supported in Allegro PCB Editor 16.6, which assigns the property ‘EMB_INDIRECT_VIA_SUPPRESS’ to the Component Definition, Component Instance, or Symbol Pin. If a component is placed on an ‘Indirect Attached’ embedded layer, this new property suppresses ALL via pads associated with the component if the PIN is not on a named net.  The indirect attach…

In this week's Whiteboard Wednesdays video, Lou Ternullo discusses DDR subsystems and their effect on latency.

https://youtu.be/7CiPHHhlj-U

One of the best, most insightful (no pun intended) conferences each year is the Embedded Vision Summit, May 12, 2015, at the Santa Clara Convention Center, not far from Cadence’s HQ offices. If you want to incorporate visual intelligence into your products, you need to go to this conference. Hot topics include convolutional neural networks, image recognition, image search, 3D vision, specialized vision processors, standards…

Consumer demand for entertainment and communication is changing the architecture of your electronic devices. And Cadence is providing key IPs necessary for SoC developers to quickly bring their products to market. Today Cadence is unveiling its first-silicon results for both DDR4 and LPDDR4 IP on TSMC's 16nm FinFET Plus (16FF+) process, with test chips operating at 3200Mbps. This speed can support the computation requirements…